Loading arch/arm64/boot/dts/qcom/qcs605.dtsi +18 −6 Original line number Diff line number Diff line Loading @@ -19,27 +19,39 @@ }; &pil_modem_mem { reg = <0 0x8b000000 0 0x3c00000>; reg = <0 0x8b000000 0 0x3e00000>; }; &pil_video_mem { reg = <0 0x8ec00000 0 0x500000>; reg = <0 0x8ee00000 0 0x500000>; }; &wlan_msa_mem { reg = <0 0x8f100000 0 0x100000>; reg = <0 0x8f300000 0 0x100000>; }; &pil_cdsp_mem { reg = <0 0x8f200000 0 0x800000>; reg = <0 0x8f400000 0 0x800000>; }; &pil_mba_mem { reg = <0 0x8fa00000 0 0x200000>; reg = <0 0x8fc00000 0 0x200000>; }; &pil_adsp_mem { reg = <0 0x8fc00000 0 0x1e00000>; reg = <0 0x8fe00000 0 0x1e00000>; }; &pil_ipa_fw_mem { reg = <0 0x91c00000 0 0x10000>; }; &pil_ipa_gsi_mem { reg = <0 0x91c10000 0 0x5000>; }; &pil_gpu_mem { reg = <0 0x91c15000 0 0x2000>; }; &soc { Loading Loading
arch/arm64/boot/dts/qcom/qcs605.dtsi +18 −6 Original line number Diff line number Diff line Loading @@ -19,27 +19,39 @@ }; &pil_modem_mem { reg = <0 0x8b000000 0 0x3c00000>; reg = <0 0x8b000000 0 0x3e00000>; }; &pil_video_mem { reg = <0 0x8ec00000 0 0x500000>; reg = <0 0x8ee00000 0 0x500000>; }; &wlan_msa_mem { reg = <0 0x8f100000 0 0x100000>; reg = <0 0x8f300000 0 0x100000>; }; &pil_cdsp_mem { reg = <0 0x8f200000 0 0x800000>; reg = <0 0x8f400000 0 0x800000>; }; &pil_mba_mem { reg = <0 0x8fa00000 0 0x200000>; reg = <0 0x8fc00000 0 0x200000>; }; &pil_adsp_mem { reg = <0 0x8fc00000 0 0x1e00000>; reg = <0 0x8fe00000 0 0x1e00000>; }; &pil_ipa_fw_mem { reg = <0 0x91c00000 0 0x10000>; }; &pil_ipa_gsi_mem { reg = <0 0x91c10000 0 0x5000>; }; &pil_gpu_mem { reg = <0 0x91c15000 0 0x2000>; }; &soc { Loading