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Commit a3a71b1e authored by Marc Zyngier's avatar Marc Zyngier Committed by Greg Kroah-Hartman
Browse files

KVM: arm/arm64: vgic-v2: Handle SGI bits in GICD_I{S,C}PENDR0 as WI 



[ Upstream commit 82e40f558de566fdee214bec68096bbd5e64a6a4 ]

A guest is not allowed to inject a SGI (or clear its pending state)
by writing to GICD_ISPENDR0 (resp. GICD_ICPENDR0), as these bits are
defined as WI (as per ARM IHI 0048B 4.3.7 and 4.3.8).

Make sure we correctly emulate the architecture.

Fixes: 96b29800 ("KVM: arm/arm64: vgic-new: Add PENDING registers handlers")
Cc: stable@vger.kernel.org # 4.7+
Reported-by: default avatarAndre Przywara <andre.przywara@arm.com>
Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Signed-off-by: default avatarWill Deacon <will@kernel.org>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent f35eb8a3

virt/kvm/arm/vgic/vgic-mmio.c

+18 −0
Original line number Diff line number Diff line
@@ -120,6 +120,12 @@ unsigned long vgic_mmio_read_pending(struct kvm_vcpu *vcpu, 
	return value;

}



static bool is_vgic_v2_sgi(struct kvm_vcpu *vcpu, struct vgic_irq *irq)

{

	return (vgic_irq_is_sgi(irq->intid) &&

		vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V2);

}



void vgic_mmio_write_spending(struct kvm_vcpu *vcpu,

			      gpa_t addr, unsigned int len,

			      unsigned long val)
@@ -130,6 +136,12 @@ void vgic_mmio_write_spending(struct kvm_vcpu *vcpu, 
	for_each_set_bit(i, &val, len * 8) {

		struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);



		/* GICD_ISPENDR0 SGI bits are WI */

		if (is_vgic_v2_sgi(vcpu, irq)) {

			vgic_put_irq(vcpu->kvm, irq);

			continue;

		}



		spin_lock(&irq->irq_lock);

		irq->pending = true;

		if (irq->config == VGIC_CONFIG_LEVEL)
@@ -150,6 +162,12 @@ void vgic_mmio_write_cpending(struct kvm_vcpu *vcpu, 
	for_each_set_bit(i, &val, len * 8) {

		struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);



		/* GICD_ICPENDR0 SGI bits are WI */

		if (is_vgic_v2_sgi(vcpu, irq)) {

			vgic_put_irq(vcpu->kvm, irq);

			continue;

		}



		spin_lock(&irq->irq_lock);



		if (irq->config == VGIC_CONFIG_LEVEL) {

virt/kvm/arm/vgic/vgic-v2.c

+4 −1
Original line number Diff line number Diff line
@@ -154,7 +154,10 @@ void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr) 
		if (vgic_irq_is_sgi(irq->intid)) {

			u32 src = ffs(irq->source);



			BUG_ON(!src);

			if (WARN_RATELIMIT(!src, "No SGI source for INTID %d\n",

					   irq->intid))

				return;



			val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;

			irq->source &= ~(1 << (src - 1));

			if (irq->source)

virt/kvm/arm/vgic/vgic-v3.c

+4 −1
Original line number Diff line number Diff line
@@ -137,7 +137,10 @@ void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr) 
		    model == KVM_DEV_TYPE_ARM_VGIC_V2) {

			u32 src = ffs(irq->source);



			BUG_ON(!src);

			if (WARN_RATELIMIT(!src, "No SGI source for INTID %d\n",

					   irq->intid))

				return;



			val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;

			irq->source &= ~(1 << (src - 1));

			if (irq->source)