Loading drivers/clk/qcom/mdss/mdss-dsi-pll-20nm.c +2 −1 Original line number Diff line number Diff line Loading @@ -603,7 +603,8 @@ int dsi_pll_clock_register_20nm(struct platform_device *pdev, mdss_dsi1_vco_clk_src.priv = pll_res; } if (pll_res->target_id == MDSS_PLL_TARGET_8994) { if ((pll_res->target_id == MDSS_PLL_TARGET_8994) || (pll_res->target_id == MDSS_PLL_TARGET_8992)) { if (pll_res->index) { rc = of_msm_clock_register(pdev->dev.of_node, mdss_dsi_pll_1_cc_8994, Loading drivers/clk/qcom/mdss/mdss-pll.c +5 −0 Original line number Diff line number Diff line Loading @@ -143,6 +143,9 @@ static int mdss_pll_resource_parse(struct platform_device *pdev, } else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_8994")) { pll_res->pll_interface_type = MDSS_DSI_PLL_20NM; pll_res->target_id = MDSS_PLL_TARGET_8994; } else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_8992")) { pll_res->pll_interface_type = MDSS_DSI_PLL_20NM; pll_res->target_id = MDSS_PLL_TARGET_8992; } else if (!strcmp(compatible_stream, "qcom,mdss_edp_pll")) { pll_res->pll_interface_type = MDSS_EDP_PLL; } else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll")) { Loading Loading @@ -388,6 +391,8 @@ static const struct of_device_id mdss_pll_dt_match[] = { {.compatible = "qcom,mdss_dsi_pll_8974"}, {.compatible = "qcom,mdss_dsi_pll_8994"}, {.compatible = "qcom,mdss_hdmi_pll_8994"}, {.compatible = "qcom,mdss_dsi_pll_8992"}, {.compatible = "qcom,mdss_hdmi_pll_8992"}, {.compatible = "qcom,mdss_dsi_pll_8916"}, {.compatible = "qcom,mdss_dsi_pll_8939"}, {.compatible = "qcom,mdss_dsi_pll_8909"}, Loading drivers/clk/qcom/mdss/mdss-pll.h +1 −0 Original line number Diff line number Diff line Loading @@ -40,6 +40,7 @@ enum { enum { MDSS_PLL_TARGET_8974, MDSS_PLL_TARGET_8994, MDSS_PLL_TARGET_8992, MDSS_PLL_TARGET_8916, MDSS_PLL_TARGET_8939, MDSS_PLL_TARGET_8909, Loading Loading
drivers/clk/qcom/mdss/mdss-dsi-pll-20nm.c +2 −1 Original line number Diff line number Diff line Loading @@ -603,7 +603,8 @@ int dsi_pll_clock_register_20nm(struct platform_device *pdev, mdss_dsi1_vco_clk_src.priv = pll_res; } if (pll_res->target_id == MDSS_PLL_TARGET_8994) { if ((pll_res->target_id == MDSS_PLL_TARGET_8994) || (pll_res->target_id == MDSS_PLL_TARGET_8992)) { if (pll_res->index) { rc = of_msm_clock_register(pdev->dev.of_node, mdss_dsi_pll_1_cc_8994, Loading
drivers/clk/qcom/mdss/mdss-pll.c +5 −0 Original line number Diff line number Diff line Loading @@ -143,6 +143,9 @@ static int mdss_pll_resource_parse(struct platform_device *pdev, } else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_8994")) { pll_res->pll_interface_type = MDSS_DSI_PLL_20NM; pll_res->target_id = MDSS_PLL_TARGET_8994; } else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_8992")) { pll_res->pll_interface_type = MDSS_DSI_PLL_20NM; pll_res->target_id = MDSS_PLL_TARGET_8992; } else if (!strcmp(compatible_stream, "qcom,mdss_edp_pll")) { pll_res->pll_interface_type = MDSS_EDP_PLL; } else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll")) { Loading Loading @@ -388,6 +391,8 @@ static const struct of_device_id mdss_pll_dt_match[] = { {.compatible = "qcom,mdss_dsi_pll_8974"}, {.compatible = "qcom,mdss_dsi_pll_8994"}, {.compatible = "qcom,mdss_hdmi_pll_8994"}, {.compatible = "qcom,mdss_dsi_pll_8992"}, {.compatible = "qcom,mdss_hdmi_pll_8992"}, {.compatible = "qcom,mdss_dsi_pll_8916"}, {.compatible = "qcom,mdss_dsi_pll_8939"}, {.compatible = "qcom,mdss_dsi_pll_8909"}, Loading
drivers/clk/qcom/mdss/mdss-pll.h +1 −0 Original line number Diff line number Diff line Loading @@ -40,6 +40,7 @@ enum { enum { MDSS_PLL_TARGET_8974, MDSS_PLL_TARGET_8994, MDSS_PLL_TARGET_8992, MDSS_PLL_TARGET_8916, MDSS_PLL_TARGET_8939, MDSS_PLL_TARGET_8909, Loading