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Commit a39533b4 authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
Browse files

drm/radeon/r600: CS parser updates 



Add some additional regs that require relocs.

Signed-off-by: default avatarAlex Deucher <alexdeucher@gmail.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 7433874e

drivers/gpu/drm/radeon/r600_cs.c

+18 −0
Original line number Diff line number Diff line
@@ -466,6 +466,23 @@ static int r600_packet3_check(struct radeon_cs_parser *p, 
		for (i = 0; i < pkt->count; i++) {

			reg = start_reg + (4 * i);

			switch (reg) {

			case SQ_ESGS_RING_BASE:

			case SQ_GSVS_RING_BASE:

			case SQ_ESTMP_RING_BASE:

			case SQ_GSTMP_RING_BASE:

			case SQ_VSTMP_RING_BASE:

			case SQ_PSTMP_RING_BASE:

			case SQ_FBUF_RING_BASE:

			case SQ_REDUC_RING_BASE:

			case SX_MEMORY_EXPORT_BASE:

				r = r600_cs_packet_next_reloc(p, &reloc);

				if (r) {

					DRM_ERROR("bad SET_CONFIG_REG "

							"0x%04X\n", reg);

					return -EINVAL;

				}

				ib[idx+1+i] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);

				break;

			case CP_COHER_BASE:

				/* use PACKET3_SURFACE_SYNC */

				return -EINVAL;
@@ -487,6 +504,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p, 
			reg = start_reg + (4 * i);

			switch (reg) {

			case DB_DEPTH_BASE:

			case DB_HTILE_DATA_BASE:

			case CB_COLOR0_BASE:

			case CB_COLOR1_BASE:

			case CB_COLOR2_BASE:

drivers/gpu/drm/radeon/r600d.h

+10 −0
Original line number Diff line number Diff line
@@ -118,6 +118,7 @@ 
#define	DB_DEBUG					0x9830

#define		PREZ_MUST_WAIT_FOR_POSTZ_DONE			(1 << 31)

#define	DB_DEPTH_BASE					0x2800C

#define	DB_HTILE_DATA_BASE				0x28014

#define	DB_WATERMARKS					0x9838

#define		DEPTH_FREE(x)					((x) << 0)

#define		DEPTH_FLUSH(x)					((x) << 5)
@@ -170,6 +171,14 @@ 
#define SQ_STACK_RESOURCE_MGMT_2                          0x8c14

#       define NUM_GS_STACK_ENTRIES(x)                    ((x) << 0)

#       define NUM_ES_STACK_ENTRIES(x)                    ((x) << 16)

#define SQ_ESGS_RING_BASE                               0x8c40

#define SQ_GSVS_RING_BASE                               0x8c48

#define SQ_ESTMP_RING_BASE                              0x8c50

#define SQ_GSTMP_RING_BASE                              0x8c58

#define SQ_VSTMP_RING_BASE                              0x8c60

#define SQ_PSTMP_RING_BASE                              0x8c68

#define SQ_FBUF_RING_BASE                               0x8c70

#define SQ_REDUC_RING_BASE                              0x8c78



#define GRBM_CNTL                                       0x8000

#       define GRBM_READ_TIMEOUT(x)                     ((x) << 0)
@@ -355,6 +364,7 @@ 




#define	SX_MISC						0x28350

#define	SX_MEMORY_EXPORT_BASE				0x9010

#define	SX_DEBUG_1					0x9054

#define		SMX_EVENT_RELEASE				(1 << 0)

#define		ENABLE_NEW_SMX_ADDRESS				(1 << 16)