Loading arch/arm/mach-omap2/cclock2420_data.c +4 −11 Original line number Diff line number Diff line Loading @@ -1025,18 +1025,12 @@ DEFINE_CLK_OMAP_MUX_GATE(iva1_ifck, "iva1_clkdm", dsp_fck_clksel, OMAP2420_EN_IVA_COP_SHIFT, &clkhwops_wait, dsp_fck_parent_names, dsp_fck_ops); DEFINE_CLK_FIXED_FACTOR(iva1_ifck_div, "iva1_ifck", &iva1_ifck, 0x0, 1, 2); static struct clk iva1_mpu_int_ifck; static const char *iva1_mpu_int_ifck_parent_names[] = { "iva1_ifck", }; static const struct clk_ops iva1_mpu_int_ifck_ops = { .init = &omap2_init_clk_clkdm, .enable = &omap2_dflt_clk_enable, .disable = &omap2_dflt_clk_disable, .is_enabled = &omap2_dflt_clk_is_enabled, .recalc_rate = &omap_fixed_divisor_recalc, "iva1_ifck_div", }; static struct clk_hw_omap iva1_mpu_int_ifck_hw = { Loading @@ -1047,11 +1041,10 @@ static struct clk_hw_omap iva1_mpu_int_ifck_hw = { .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT, .clkdm_name = "iva1_clkdm", .fixed_div = 2, }; DEFINE_STRUCT_CLK(iva1_mpu_int_ifck, iva1_mpu_int_ifck_parent_names, iva1_mpu_int_ifck_ops); aes_ick_ops); static struct clk mailboxes_ick; Loading arch/arm/mach-omap2/clock.c +0 −21 Original line number Diff line number Diff line Loading @@ -81,27 +81,6 @@ u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg) return val; } /* * Used for clocks that have the same value as the parent clock, * divided by some factor */ unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw, unsigned long parent_rate) { struct clk_hw_omap *oclk; if (!hw) { pr_warn("%s: hw is NULL\n", __func__); return -EINVAL; } oclk = to_clk_hw_omap(hw); WARN_ON(!oclk->fixed_div); return parent_rate / oclk->fixed_div; } /* * OMAP2+ specific clock functions */ Loading arch/arm/mach-omap2/clock.h +0 −3 Original line number Diff line number Diff line Loading @@ -178,9 +178,6 @@ struct clksel { const struct clksel_rate *rates; }; unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw, unsigned long parent_rate); /* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */ #define CORE_CLK_SRC_32K 0x0 #define CORE_CLK_SRC_DPLL 0x1 Loading Loading
arch/arm/mach-omap2/cclock2420_data.c +4 −11 Original line number Diff line number Diff line Loading @@ -1025,18 +1025,12 @@ DEFINE_CLK_OMAP_MUX_GATE(iva1_ifck, "iva1_clkdm", dsp_fck_clksel, OMAP2420_EN_IVA_COP_SHIFT, &clkhwops_wait, dsp_fck_parent_names, dsp_fck_ops); DEFINE_CLK_FIXED_FACTOR(iva1_ifck_div, "iva1_ifck", &iva1_ifck, 0x0, 1, 2); static struct clk iva1_mpu_int_ifck; static const char *iva1_mpu_int_ifck_parent_names[] = { "iva1_ifck", }; static const struct clk_ops iva1_mpu_int_ifck_ops = { .init = &omap2_init_clk_clkdm, .enable = &omap2_dflt_clk_enable, .disable = &omap2_dflt_clk_disable, .is_enabled = &omap2_dflt_clk_is_enabled, .recalc_rate = &omap_fixed_divisor_recalc, "iva1_ifck_div", }; static struct clk_hw_omap iva1_mpu_int_ifck_hw = { Loading @@ -1047,11 +1041,10 @@ static struct clk_hw_omap iva1_mpu_int_ifck_hw = { .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT, .clkdm_name = "iva1_clkdm", .fixed_div = 2, }; DEFINE_STRUCT_CLK(iva1_mpu_int_ifck, iva1_mpu_int_ifck_parent_names, iva1_mpu_int_ifck_ops); aes_ick_ops); static struct clk mailboxes_ick; Loading
arch/arm/mach-omap2/clock.c +0 −21 Original line number Diff line number Diff line Loading @@ -81,27 +81,6 @@ u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg) return val; } /* * Used for clocks that have the same value as the parent clock, * divided by some factor */ unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw, unsigned long parent_rate) { struct clk_hw_omap *oclk; if (!hw) { pr_warn("%s: hw is NULL\n", __func__); return -EINVAL; } oclk = to_clk_hw_omap(hw); WARN_ON(!oclk->fixed_div); return parent_rate / oclk->fixed_div; } /* * OMAP2+ specific clock functions */ Loading
arch/arm/mach-omap2/clock.h +0 −3 Original line number Diff line number Diff line Loading @@ -178,9 +178,6 @@ struct clksel { const struct clksel_rate *rates; }; unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw, unsigned long parent_rate); /* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */ #define CORE_CLK_SRC_32K 0x0 #define CORE_CLK_SRC_DPLL 0x1 Loading