Merge "Merge remote-tracking branch '4.9/tmp-6856581' into msm-4.9" into msm-4.9 (a3107ff4) · Commits · e / devices / android_kernel_fairphone_FP3

Makefile

+1 −1

Original line number	Diff line number	Diff line
		VERSION = 4
		PATCHLEVEL = 9
		SUBLEVEL = 20
		SUBLEVEL = 21
		EXTRAVERSION =
		NAME = Roaring Lionus

arch/arm/boot/dts/bcm5301x.dtsi

+2 −2

Original line number	Diff line number	Diff line
		@@ -66,14 +66,14 @@
		timer@20200 {
		compatible = "arm,cortex-a9-global-timer";
		reg = <0x20200 0x100>;
		interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
		interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
		clocks = <&periph_clk>;
		};

		local-timer@20600 {
		compatible = "arm,cortex-a9-twd-timer";
		reg = <0x20600 0x100>;
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
		interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE_RISING>;
		clocks = <&periph_clk>;
		};

arch/arm/mach-bcm/bcm_5301x.c

+28 −0

Original line number	Diff line number	Diff line
		@@ -9,14 +9,42 @@
		#include <asm/hardware/cache-l2x0.h>

		#include <asm/mach/arch.h>
		#include <asm/siginfo.h>
		#include <asm/signal.h>

		#define FSR_EXTERNAL (1 << 12)
		#define FSR_READ (0 << 10)
		#define FSR_IMPRECISE 0x0406

		static const char *const bcm5301x_dt_compat[] __initconst = {
		"brcm,bcm4708",
		NULL,
		};

		static int bcm5301x_abort_handler(unsigned long addr, unsigned int fsr,
		struct pt_regs *regs)
		{
		/*
		* We want to ignore aborts forwarded from the PCIe bus that are
		* expected and shouldn't really be passed by the PCIe controller.
		* The biggest disadvantage is the same FSR code may be reported when
		* reading non-existing APB register and we shouldn't ignore that.
		*/
		if (fsr == (FSR_EXTERNAL \| FSR_READ \| FSR_IMPRECISE))
		return 0;

		return 1;
		}

		static void __init bcm5301x_init_early(void)
		{
		hook_fault_code(16 + 6, bcm5301x_abort_handler, SIGBUS, BUS_OBJERR,
		"imprecise external abort");
		}

		DT_MACHINE_START(BCM5301X, "BCM5301X")
		.l2c_aux_val = 0,
		.l2c_aux_mask = ~0,
		.dt_compat = bcm5301x_dt_compat,
		.init_early = bcm5301x_init_early,
		MACHINE_END

arch/mips/lantiq/irq.c

+17 −21

Original line number	Diff line number	Diff line
		@@ -269,6 +269,11 @@ static void ltq_hw5_irqdispatch(void)
		DEFINE_HWx_IRQDISPATCH(5)
		#endif

		static void ltq_hw_irq_handler(struct irq_desc *desc)
		{
		ltq_hw_irqdispatch(irq_desc_get_irq(desc) - 2);
		}

		#ifdef CONFIG_MIPS_MT_SMP
		void __init arch_init_ipiirq(int irq, struct irqaction *action)
		{
		@@ -313,23 +318,19 @@ static struct irqaction irq_call = {
		asmlinkage void plat_irq_dispatch(void)
		{
		unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
		unsigned int i;
		int irq;

		if ((MIPS_CPU_TIMER_IRQ == 7) && (pending & CAUSEF_IP7)) {
		do_IRQ(MIPS_CPU_TIMER_IRQ);
		goto out;
		} else {
		for (i = 0; i < MAX_IM; i++) {
		if (pending & (CAUSEF_IP2 << i)) {
		ltq_hw_irqdispatch(i);
		goto out;
		}
		}
		if (!pending) {
		spurious_interrupt();
		return;
		}
		pr_alert("Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());

		out:
		return;
		pending >>= CAUSEB_IP;
		while (pending) {
		irq = fls(pending) - 1;
		do_IRQ(MIPS_CPU_IRQ_BASE + irq);
		pending &= ~BIT(irq);
		}
		}

		static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
		@@ -354,11 +355,6 @@ static const struct irq_domain_ops irq_domain_ops = {
		.map = icu_map,
		};

		static struct irqaction cascade = {
		.handler = no_action,
		.name = "cascade",
		};

		int __init icu_of_init(struct device_node node, struct device_node parent)
		{
		struct device_node *eiu_node;
		@@ -390,7 +386,7 @@ int __init icu_of_init(struct device_node node, struct device_node parent)
		mips_cpu_irq_init();

		for (i = 0; i < MAX_IM; i++)
		setup_irq(i + 2, &cascade);
		irq_set_chained_handler(i + 2, ltq_hw_irq_handler);

		if (cpu_has_vint) {
		pr_info("Setting up vectored interrupts\n");

arch/parisc/include/asm/uaccess.h

+34 −25

Original line number	Diff line number	Diff line
		@@ -67,6 +67,15 @@ struct exception_table_entry {
		".word (" #fault_addr " - .), (" #except_addr " - .)\n\t" \
		".previous\n"

		/*
		* ASM_EXCEPTIONTABLE_ENTRY_EFAULT() creates a special exception table entry
		* (with lowest bit set) for which the fault handler in fixup_exception() will
		* load -EFAULT into %r8 for a read or write fault, and zeroes the target
		* register in case of a read fault in get_user().
		*/
		#define ASM_EXCEPTIONTABLE_ENTRY_EFAULT( fault_addr, except_addr )\
		ASM_EXCEPTIONTABLE_ENTRY( fault_addr, except_addr + 1)

		/*
		* The page fault handler stores, in a per-cpu area, the following information
		* if a fixup routine is available.
		@@ -94,7 +103,7 @@ struct exception_data {
		#define __get_user(x, ptr) \
		({ \
		register long __gu_err __asm__ ("r8") = 0; \
		register long __gu_val __asm__ ("r9") = 0; \
		register long __gu_val; \
		\
		load_sr2(); \
		switch (sizeof(*(ptr))) { \
		@@ -110,22 +119,23 @@ struct exception_data {
		})

		#define __get_user_asm(ldx, ptr) \
		__asm__("\n1:\t" ldx "\t0(%%sr2,%2),%0\n\t" \
		ASM_EXCEPTIONTABLE_ENTRY(1b, fixup_get_user_skip_1)\
		__asm__("1: " ldx " 0(%%sr2,%2),%0\n" \
		"9:\n" \
		ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 9b) \
		: "=r"(__gu_val), "=r"(__gu_err) \
		: "r"(ptr), "1"(__gu_err) \
		: "r1");
		: "r"(ptr), "1"(__gu_err));

		#if !defined(CONFIG_64BIT)

		#define __get_user_asm64(ptr) \
		__asm__("\n1:\tldw 0(%%sr2,%2),%0" \
		"\n2:\tldw 4(%%sr2,%2),%R0\n\t" \
		ASM_EXCEPTIONTABLE_ENTRY(1b, fixup_get_user_skip_2)\
		ASM_EXCEPTIONTABLE_ENTRY(2b, fixup_get_user_skip_1)\
		__asm__(" copy %%r0,%R0\n" \
		"1: ldw 0(%%sr2,%2),%0\n" \
		"2: ldw 4(%%sr2,%2),%R0\n" \
		"9:\n" \
		ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 9b) \
		ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 9b) \
		: "=r"(__gu_val), "=r"(__gu_err) \
		: "r"(ptr), "1"(__gu_err) \
		: "r1");
		: "r"(ptr), "1"(__gu_err));

		#endif /* !defined(CONFIG_64BIT) */

		@@ -151,32 +161,31 @@ struct exception_data {
		* The "__put_user/kernel_asm()" macros tell gcc they read from memory
		* instead of writing. This is because they do not write to any memory
		* gcc knows about, so there are no aliasing issues. These macros must
		* also be aware that "fixup_put_user_skip_[12]" are executed in the
		* context of the fault, and any registers used there must be listed
		* as clobbers. In this case only "r1" is used by the current routines.
		* r8/r9 are already listed as err/val.
		* also be aware that fixups are executed in the context of the fault,
		* and any registers used there must be listed as clobbers.
		* r8 is already listed as err.
		*/

		#define __put_user_asm(stx, x, ptr) \
		__asm__ __volatile__ ( \
		"\n1:\t" stx "\t%2,0(%%sr2,%1)\n\t" \
		ASM_EXCEPTIONTABLE_ENTRY(1b, fixup_put_user_skip_1)\
		"1: " stx " %2,0(%%sr2,%1)\n" \
		"9:\n" \
		ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 9b) \
		: "=r"(__pu_err) \
		: "r"(ptr), "r"(x), "0"(__pu_err) \
		: "r1")
		: "r"(ptr), "r"(x), "0"(__pu_err))


		#if !defined(CONFIG_64BIT)

		#define __put_user_asm64(__val, ptr) do { \
		__asm__ __volatile__ ( \
		"\n1:\tstw %2,0(%%sr2,%1)" \
		"\n2:\tstw %R2,4(%%sr2,%1)\n\t" \
		ASM_EXCEPTIONTABLE_ENTRY(1b, fixup_put_user_skip_2)\
		ASM_EXCEPTIONTABLE_ENTRY(2b, fixup_put_user_skip_1)\
		"1: stw %2,0(%%sr2,%1)\n" \
		"2: stw %R2,4(%%sr2,%1)\n" \
		"9:\n" \
		ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 9b) \
		ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 9b) \
		: "=r"(__pu_err) \
		: "r"(ptr), "r"(__val), "0"(__pu_err) \
		: "r1"); \
		: "r"(ptr), "r"(__val), "0"(__pu_err)); \
		} while (0)

		#endif /* !defined(CONFIG_64BIT) */