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Commit a2f7a9ce authored by Anton Blanchard's avatar Anton Blanchard Committed by Linus Torvalds
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[PATCH] ppc64: Fix runlatch code to work on pseries machines 



Not all ppc64 CPUs have the CTRL SPR, so we need a cputable feature for it.

Signed-off-by: default avatarAnton Blanchard <anton@samba.org>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent 315a6998

arch/ppc64/kernel/cputable.c

+4 −4
Original line number Diff line number Diff line
@@ -81,7 +81,7 @@ struct cpu_spec cpu_specs[] = { 
		.cpu_name		= "RS64-II (northstar)",

		.cpu_features		= CPU_FTR_SPLIT_ID_CACHE |

			CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |

			CPU_FTR_PMC8 | CPU_FTR_MMCRA,

			CPU_FTR_PMC8 | CPU_FTR_MMCRA | CPU_FTR_CTRL,

		.cpu_user_features	= COMMON_USER_PPC64,

		.icache_bsize		= 128,

		.dcache_bsize		= 128,
@@ -94,7 +94,7 @@ struct cpu_spec cpu_specs[] = { 
		.cpu_name		= "RS64-III (pulsar)",

		.cpu_features		= CPU_FTR_SPLIT_ID_CACHE |

			CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |

			CPU_FTR_PMC8 | CPU_FTR_MMCRA,

			CPU_FTR_PMC8 | CPU_FTR_MMCRA | CPU_FTR_CTRL,

		.cpu_user_features	= COMMON_USER_PPC64,

		.icache_bsize		= 128,

		.dcache_bsize		= 128,
@@ -107,7 +107,7 @@ struct cpu_spec cpu_specs[] = { 
		.cpu_name		= "RS64-III (icestar)",

		.cpu_features		= CPU_FTR_SPLIT_ID_CACHE |

			CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |

			CPU_FTR_PMC8 | CPU_FTR_MMCRA,

			CPU_FTR_PMC8 | CPU_FTR_MMCRA | CPU_FTR_CTRL,

		.cpu_user_features	= COMMON_USER_PPC64,

		.icache_bsize		= 128,

		.dcache_bsize		= 128,
@@ -120,7 +120,7 @@ struct cpu_spec cpu_specs[] = { 
		.cpu_name		= "RS64-IV (sstar)",

		.cpu_features		= CPU_FTR_SPLIT_ID_CACHE |

			CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |

			CPU_FTR_PMC8 | CPU_FTR_MMCRA,

			CPU_FTR_PMC8 | CPU_FTR_MMCRA | CPU_FTR_CTRL,

		.cpu_user_features	= COMMON_USER_PPC64,

		.icache_bsize		= 128,

		.dcache_bsize		= 128,

include/asm-ppc64/cputable.h

+2 −1
Original line number Diff line number Diff line
@@ -138,6 +138,7 @@ extern firmware_feature_t firmware_features_table[]; 
#define CPU_FTR_COHERENT_ICACHE  	ASM_CONST(0x0000020000000000)

#define CPU_FTR_LOCKLESS_TLBIE		ASM_CONST(0x0000040000000000)

#define CPU_FTR_MMCRA_SIHV		ASM_CONST(0x0000080000000000)

#define CPU_FTR_CTRL			ASM_CONST(0x0000100000000000)



/* Platform firmware features */

#define FW_FTR_				ASM_CONST(0x0000000000000001)
@@ -148,7 +149,7 @@ extern firmware_feature_t firmware_features_table[]; 


#define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \

                                 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \

                                 CPU_FTR_NODSISRALIGN)

                                 CPU_FTR_NODSISRALIGN | CPU_FTR_CTRL)



/* iSeries doesn't support large pages */

#ifdef CONFIG_PPC_ISERIES

include/asm-ppc64/processor.h

+11 −6
Original line number Diff line number Diff line
@@ -20,6 +20,7 @@ 
#include <asm/ptrace.h>

#include <asm/types.h>

#include <asm/systemcfg.h>

#include <asm/cputable.h>



/* Machine State Register (MSR) Fields */

#define MSR_SF_LG	63              /* Enable 64 bit mode */
@@ -501,19 +502,23 @@ static inline void ppc64_runlatch_on(void) 
{

	unsigned long ctrl;



	if (cpu_has_feature(CPU_FTR_CTRL)) {

		ctrl = mfspr(SPRN_CTRLF);

		ctrl |= CTRL_RUNLATCH;

		mtspr(SPRN_CTRLT, ctrl);

	}

}



static inline void ppc64_runlatch_off(void)

{

	unsigned long ctrl;



	if (cpu_has_feature(CPU_FTR_CTRL)) {

		ctrl = mfspr(SPRN_CTRLF);

		ctrl &= ~CTRL_RUNLATCH;

		mtspr(SPRN_CTRLT, ctrl);

	}

}



#endif /* __KERNEL__ */