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Commit a1aed681 authored by Syed Rameez Mustafa's avatar Syed Rameez Mustafa
Browse files

ARM: dts: msm: Add efficiency values for all SDM845 CPUs 



This is used by the scheduler to distinguish between the silver
and gold clusters.

Change-Id: I5e886054e0ba23b08fb530d86c6c21741d12a585
Signed-off-by: default avatarSyed Rameez Mustafa <rameezmustafa@codeaurora.org>
parent defea4e8

arch/arm64/boot/dts/qcom/sdm845.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -42,6 +42,7 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x0>;

			enable-method = "psci";

			efficiency = <1024>;

			cache-size = <0x8000>;

			cpu-release-addr = <0x0 0x90000000>;

			next-level-cache = <&L2_0>;
@@ -72,6 +73,7 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x100>;

			enable-method = "psci";

			efficiency = <1024>;

			cache-size = <0x8000>;

			cpu-release-addr = <0x0 0x90000000>;

			next-level-cache = <&L2_1>;
@@ -96,6 +98,7 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x200>;

			enable-method = "psci";

			efficiency = <1024>;

			cache-size = <0x8000>;

			cpu-release-addr = <0x0 0x90000000>;

			next-level-cache = <&L2_2>;
@@ -120,6 +123,7 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x300>;

			enable-method = "psci";

			efficiency = <1024>;

			cache-size = <0x8000>;

			cpu-release-addr = <0x0 0x90000000>;

			next-level-cache = <&L2_3>;
@@ -144,6 +148,7 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x400>;

			enable-method = "psci";

			efficiency = <1740>;

			cache-size = <0x20000>;

			cpu-release-addr = <0x0 0x90000000>;

			next-level-cache = <&L2_4>;
@@ -168,6 +173,7 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x500>;

			enable-method = "psci";

			efficiency = <1740>;

			cache-size = <0x20000>;

			cpu-release-addr = <0x0 0x90000000>;

			next-level-cache = <&L2_5>;
@@ -192,6 +198,7 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x600>;

			enable-method = "psci";

			efficiency = <1740>;

			cache-size = <0x20000>;

			cpu-release-addr = <0x0 0x90000000>;

			next-level-cache = <&L2_6>;
@@ -216,6 +223,7 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x700>;

			enable-method = "psci";

			efficiency = <1740>;

			cache-size = <0x20000>;

			cpu-release-addr = <0x0 0x90000000>;

			next-level-cache = <&L2_7>;