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Commit a1a4b78b authored by Abhijit Kulkarni's avatar Abhijit Kulkarni Committed by Veera Sundaram Sankaran
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drm/msm/sde: cleanup handling of secure buffer in planes 



This change handles the fb_translation mode property cleanly.
Plane reads this property only if the dirty bit is set. To accomplish
the correct HW programming, this change separates
the hw programming of the secure buffers in a separate function.

CRs-Fixed: 2064272
Change-Id: I05bcb6addabdedfed22c16854372eea5a61f1ade
Signed-off-by: default avatarAbhijit Kulkarni <kabhijit@codeaurora.org>
parent 1b3340c4

drivers/gpu/drm/msm/sde/sde_hw_sspp.c

+30 −10
Original line number Diff line number Diff line
@@ -314,7 +314,6 @@ static void sde_hw_sspp_setup_format(struct sde_hw_pipe *ctx, 
{

	struct sde_hw_blk_reg_map *c;

	u32 chroma_samp, unpack, src_format;

	u32 secure = 0, secure_bit_mask;

	u32 opmode = 0;

	u32 fast_clear = 0;

	u32 op_mode_off, unpack_pat_off, format_off;
@@ -327,12 +326,10 @@ static void sde_hw_sspp_setup_format(struct sde_hw_pipe *ctx, 
		op_mode_off = SSPP_SRC_OP_MODE;

		unpack_pat_off = SSPP_SRC_UNPACK_PATTERN;

		format_off = SSPP_SRC_FORMAT;

		secure_bit_mask = (rect_mode == SDE_SSPP_RECT_SOLO) ? 0xF : 0x5;

	} else {

		op_mode_off = SSPP_SRC_OP_MODE_REC1;

		unpack_pat_off = SSPP_SRC_UNPACK_PATTERN_REC1;

		format_off = SSPP_SRC_FORMAT_REC1;

		secure_bit_mask = 0xA;

	}



	c = &ctx->hw;
@@ -340,12 +337,6 @@ static void sde_hw_sspp_setup_format(struct sde_hw_pipe *ctx, 
	opmode &= ~(MDSS_MDP_OP_FLIP_LR | MDSS_MDP_OP_FLIP_UD |

			MDSS_MDP_OP_BWC_EN | MDSS_MDP_OP_PE_OVERRIDE);



	secure = SDE_REG_READ(c, SSPP_SRC_ADDR_SW_STATUS + idx);

	if (flags & SDE_SSPP_SECURE_OVERLAY_SESSION)

		secure |= secure_bit_mask;

	else

		secure &= ~secure_bit_mask;



	if (flags & SDE_SSPP_FLIP_LR)

		opmode |= MDSS_MDP_OP_FLIP_LR;

	if (flags & SDE_SSPP_FLIP_UD)
@@ -415,12 +406,40 @@ static void sde_hw_sspp_setup_format(struct sde_hw_pipe *ctx, 
	SDE_REG_WRITE(c, format_off + idx, src_format);

	SDE_REG_WRITE(c, unpack_pat_off + idx, unpack);

	SDE_REG_WRITE(c, op_mode_off + idx, opmode);

	SDE_REG_WRITE(c, SSPP_SRC_ADDR_SW_STATUS + idx, secure);



	/* clear previous UBWC error */

	SDE_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS + idx, BIT(31));

}



static void sde_hw_sspp_setup_secure(struct sde_hw_pipe *ctx,

		enum sde_sspp_multirect_index rect_mode,

		bool enable)

{

	struct sde_hw_blk_reg_map *c;

	u32 secure = 0, secure_bit_mask;

	u32 idx;



	if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx))

		return;



	if (rect_mode == SDE_SSPP_RECT_SOLO || rect_mode == SDE_SSPP_RECT_0)

		secure_bit_mask = (rect_mode == SDE_SSPP_RECT_SOLO) ? 0xF :

			0x5;

	else

		secure_bit_mask = 0xA;



	c = &ctx->hw;



	secure = SDE_REG_READ(c, SSPP_SRC_ADDR_SW_STATUS + idx);

	if (enable)

		secure |= secure_bit_mask;

	else

		secure &= ~secure_bit_mask;



	SDE_REG_WRITE(c, SSPP_SRC_ADDR_SW_STATUS + idx, secure);

}





static void sde_hw_sspp_setup_pe_config(struct sde_hw_pipe *ctx,

		struct sde_hw_pixel_ext *pe_ext)

{
@@ -1153,6 +1172,7 @@ static void _setup_layer_ops(struct sde_hw_pipe *c, 
		c->ops.setup_sourceaddress = sde_hw_sspp_setup_sourceaddress;

		c->ops.setup_solidfill = sde_hw_sspp_setup_solidfill;

		c->ops.setup_pe = sde_hw_sspp_setup_pe_config;

		c->ops.setup_secure_address = sde_hw_sspp_setup_secure;

	}



	if (test_bit(SDE_SSPP_EXCL_RECT, &features))

drivers/gpu/drm/msm/sde/sde_hw_sspp.h

+10 −0
Original line number Diff line number Diff line
@@ -613,6 +613,16 @@ struct sde_hw_sspp_ops { 
	 */

	void (*setup_cdp)(struct sde_hw_pipe *ctx,

			struct sde_hw_pipe_cdp_cfg *cfg);



	/**

	 * setup_secure_address - setup secureity status of the source address

	 * @ctx: Pointer to pipe context

	 * @index: rectangle index in multirect

	 * @enable: enable content protected buffer state

	 */

	void (*setup_secure_address)(struct sde_hw_pipe *ctx,

			enum sde_sspp_multirect_index index,

		bool enable);

};



/**

drivers/gpu/drm/msm/sde/sde_plane.c

+16 −8
Original line number Diff line number Diff line
@@ -3205,7 +3205,7 @@ void sde_plane_set_error(struct drm_plane *plane, bool error) 
static int sde_plane_sspp_atomic_update(struct drm_plane *plane,

				struct drm_plane_state *old_state)

{

	uint32_t nplanes, src_flags = 0x0;

	uint32_t nplanes, src_flags;

	struct sde_plane *psde;

	struct drm_plane_state *state;

	struct sde_plane_state *pstate;
@@ -3218,7 +3218,6 @@ static int sde_plane_sspp_atomic_update(struct drm_plane *plane, 
	const struct sde_rect *crtc_roi;

	bool q16_data = true;

	int idx;

	int mode;



	if (!plane) {

		SDE_ERROR("invalid plane\n");
@@ -3352,10 +3351,19 @@ static int sde_plane_sspp_atomic_update(struct drm_plane *plane, 
	_sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);



	/* update secure session flag */

	mode = sde_plane_get_property(pstate, PLANE_PROP_FB_TRANSLATION_MODE);

	if (pstate->dirty & SDE_PLANE_DIRTY_FB_TRANSLATION_MODE) {

		bool enable = false;

		int mode = sde_plane_get_property(pstate,

				PLANE_PROP_FB_TRANSLATION_MODE);



		if ((mode == SDE_DRM_FB_SEC) ||

				(mode == SDE_DRM_FB_SEC_DIR_TRANS))

		src_flags |= SDE_SSPP_SECURE_OVERLAY_SESSION;

			enable = true;

		/* update secure session flag */

		psde->pipe_hw->ops.setup_secure_address(psde->pipe_hw,

				pstate->multirect_index,

				enable);

	}



	/* update roi config */

	if (pstate->dirty & SDE_PLANE_DIRTY_RECTS) {
@@ -3434,9 +3442,9 @@ static int sde_plane_sspp_atomic_update(struct drm_plane *plane, 
					pstate->multirect_mode);

	}



	if (((pstate->dirty & SDE_PLANE_DIRTY_FORMAT) ||

			(src_flags & SDE_SSPP_SECURE_OVERLAY_SESSION)) &&

	if ((pstate->dirty & SDE_PLANE_DIRTY_FORMAT) &&

			psde->pipe_hw->ops.setup_format) {

		src_flags = 0x0;

		SDE_DEBUG_PLANE(psde, "rotation 0x%X\n", rstate->out_rotation);

		if (rstate->out_rotation & DRM_REFLECT_X)

			src_flags |= SDE_SSPP_FLIP_LR;