x86: Clean up mtrr/generic.c

/* This only handles 32bit MTRR on 32bit hosts. This is strictly wrong

   because MTRRs can span upto 40 bits (36bits on most modern x86) */ 

/*

 * This only handles 32bit MTRR on 32bit hosts. This is strictly wrong

 * because MTRRs can span upto 40 bits (36bits on most modern x86)

 */

#define DEBUG

#include <linux/module.h>

#include <linux/init.h>

#include <linux/slab.h>

#include <linux/io.h>

#include <linux/mm.h>

#include <linux/module.h>

#include <asm/io.h>

#include <asm/mtrr.h>

#include <asm/msr.h>

#include <asm/system.h>

#include <asm/cpufeature.h>

#include <asm/processor-flags.h>

#include <asm/cpufeature.h>

#include <asm/tlbflush.h>

#include <asm/system.h>

#include <asm/mtrr.h>

#include <asm/msr.h>

#include <asm/pat.h>

#include "mtrr.h"

struct fixed_range_block {

static int mtrr_state_set;

u64 mtrr_tom2;

struct mtrr_state_type mtrr_state = {};

struct mtrr_state_type mtrr_state;

EXPORT_SYMBOL_GPL(mtrr_state);

/**

/*

 * BIOS is expected to clear MtrrFixDramModEn bit, see for example

 * "BIOS and Kernel Developer's Guide for the AMD Athlon 64 and AMD

 * Opteron Processors" (26094 Rev. 3.30 February 2006), section

	 * Look of multiple ranges matching this address and pick type

	 * as per MTRR precedence

	 */

	if (!(mtrr_state.enabled & 2)) {

	if (!(mtrr_state.enabled & 2))

		return mtrr_state.def_type;

	}

	prev_match = 0xFF;

	for (i = 0; i < num_var_ranges; ++i) {

		if (start_state != end_state)

			return 0xFE;

		if ((start & mask) != (base & mask)) {

		if ((start & mask) != (base & mask))

			continue;

		}

		curr_match = mtrr_state.var_ranges[i].base_lo & 0xff;

		if (prev_match == 0xFF) {

			curr_match = MTRR_TYPE_WRTHROUGH;

		}

		if (prev_match != curr_match) {

		if (prev_match != curr_match)

			return MTRR_TYPE_UNCACHABLE;

	}

	}

	if (mtrr_tom2) {

		if (start >= (1ULL<<32) && (end < mtrr_tom2))

	rdmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi);

}

/*  fill the MSR pair relating to a var range  */

/* Fill the MSR pair relating to a var range */

void fill_mtrr_var_range(unsigned int index,

		u32 base_lo, u32 base_hi, u32 mask_lo, u32 mask_hi)

{

	vr[index].mask_hi = mask_hi;

}

static void

get_fixed_ranges(mtrr_type * frs)

static void get_fixed_ranges(mtrr_type *frs)

{

	unsigned int *p = (unsigned int *)frs;

	int i;

	if (!last_fixed_end)

		return;

	printk(KERN_DEBUG "  %05X-%05X %s\n", last_fixed_start,

	pr_debug("  %05X-%05X %s\n", last_fixed_start,

		 last_fixed_end - 1, mtrr_attrib_to_str(last_fixed_type));

	last_fixed_end = 0;

	last_fixed_type = type;

}

static void __init print_fixed(unsigned base, unsigned step,

			       const mtrr_type *types)

static void __init

print_fixed(unsigned base, unsigned step, const mtrr_type *types)

{

	unsigned i;

	unsigned int i;

	int high_width;

	printk(KERN_DEBUG "MTRR default type: %s\n",

	pr_debug("MTRR default type: %s\n",

		 mtrr_attrib_to_str(mtrr_state.def_type));

	if (mtrr_state.have_fixed) {

		printk(KERN_DEBUG "MTRR fixed ranges %sabled:\n",

		pr_debug("MTRR fixed ranges %sabled:\n",

			 mtrr_state.enabled & 1 ? "en" : "dis");

		print_fixed(0x00000, 0x10000, mtrr_state.fixed_ranges + 0);

		for (i = 0; i < 2; ++i)

			print_fixed(0x80000 + i * 0x20000, 0x04000, mtrr_state.fixed_ranges + (i + 1) * 8);

			print_fixed(0x80000 + i * 0x20000, 0x04000,

				    mtrr_state.fixed_ranges + (i + 1) * 8);

		for (i = 0; i < 8; ++i)

			print_fixed(0xC0000 + i * 0x08000, 0x01000, mtrr_state.fixed_ranges + (i + 3) * 8);

			print_fixed(0xC0000 + i * 0x08000, 0x01000,

				    mtrr_state.fixed_ranges + (i + 3) * 8);

		/* tail */

		print_fixed_last();

	}

	printk(KERN_DEBUG "MTRR variable ranges %sabled:\n",

	pr_debug("MTRR variable ranges %sabled:\n",

		 mtrr_state.enabled & 2 ? "en" : "dis");

	if (size_or_mask & 0xffffffffUL)

		high_width = ffs(size_or_mask & 0xffffffffUL) - 1;

	else

		high_width = ffs(size_or_mask>>32) + 32 - 1;

	high_width = (high_width - (32 - PAGE_SHIFT) + 3) / 4;

	for (i = 0; i < num_var_ranges; ++i) {

		if (mtrr_state.var_ranges[i].mask_lo & (1 << 11))

			printk(KERN_DEBUG "  %u base %0*X%05X000 mask %0*X%05X000 %s\n",

			pr_debug("  %u base %0*X%05X000 mask %0*X%05X000 %s\n",

				 i,

				 high_width,

				 mtrr_state.var_ranges[i].base_hi,

				 mtrr_state.var_ranges[i].mask_lo >> 12,

				 mtrr_attrib_to_str(mtrr_state.var_ranges[i].base_lo & 0xff));

		else

			printk(KERN_DEBUG "  %u disabled\n", i);

	}

	if (mtrr_tom2) {

		printk(KERN_DEBUG "TOM2: %016llx aka %lldM\n",

				  mtrr_tom2, mtrr_tom2>>20);

			pr_debug("  %u disabled\n", i);

	}

	if (mtrr_tom2)

		pr_debug("TOM2: %016llx aka %lldM\n", mtrr_tom2, mtrr_tom2>>20);

}

/* Grab all of the MTRR state for this CPU into *state */

void __init get_mtrr_state(void)

{

	unsigned int i;

	struct mtrr_var_range *vrs;

	unsigned lo, dummy;

	unsigned long flags;

	unsigned lo, dummy;

	unsigned int i;

	vrs = mtrr_state.var_ranges;

	if (amd_special_default_mtrr()) {

		unsigned low, high;

		/* TOP_MEM2 */

		rdmsr(MSR_K8_TOP_MEM2, low, high);

		mtrr_tom2 = high;

	post_set();

	local_irq_restore(flags);

}

/*  Some BIOS's are fucked and don't set all MTRRs the same!  */

/* Some BIOS's are messed up and don't set all MTRRs the same! */

void __init mtrr_state_warn(void)

{

	unsigned long mask = smp_changes_mask;

	if (!mask)

		return;

	if (mask & MTRR_CHANGE_MASK_FIXED)

		printk(KERN_WARNING "mtrr: your CPUs had inconsistent fixed MTRR settings\n");

		pr_warning("mtrr: your CPUs had inconsistent fixed MTRR settings\n");

	if (mask & MTRR_CHANGE_MASK_VARIABLE)

		printk(KERN_WARNING "mtrr: your CPUs had inconsistent variable MTRR settings\n");

		pr_warning("mtrr: your CPUs had inconsistent variable MTRR settings\n");

	if (mask & MTRR_CHANGE_MASK_DEFTYPE)

		printk(KERN_WARNING "mtrr: your CPUs had inconsistent MTRRdefType settings\n");

		pr_warning("mtrr: your CPUs had inconsistent MTRRdefType settings\n");

	printk(KERN_INFO "mtrr: probably your BIOS does not setup all CPUs.\n");

	printk(KERN_INFO "mtrr: corrected configuration.\n");

}

/* Doesn't attempt to pass an error out to MTRR users

   because it's quite complicated in some cases and probably not

   worth it because the best error handling is to ignore it. */

/*

 * Doesn't attempt to pass an error out to MTRR users

 * because it's quite complicated in some cases and probably not

 * worth it because the best error handling is to ignore it.

 */

void mtrr_wrmsr(unsigned msr, unsigned a, unsigned b)

{

	if (wrmsr_safe(msr, a, b) < 0)

	if (wrmsr_safe(msr, a, b) < 0) {

		printk(KERN_ERR

			"MTRR: CPU %u: Writing MSR %x to %x:%x failed\n",

			smp_processor_id(), msr, a, b);

	}

}

/**

 * set_fixed_range - checks & updates a fixed-range MTRR if it differs from the value it should have

 * set_fixed_range - checks & updates a fixed-range MTRR if it

 *		     differs from the value it should have

 * @msr: MSR address of the MTTR which should be checked and updated

 * @changed: pointer which indicates whether the MTRR needed to be changed

 * @msrwords: pointer to the MSR values which the MSR should have

 *

 * Returns: The index of the region on success, else negative on error.

 */

int generic_get_free_region(unsigned long base, unsigned long size, int replace_reg)

int

generic_get_free_region(unsigned long base, unsigned long size, int replace_reg)

{

	int i, max;

	mtrr_type ltype;

	unsigned long lbase, lsize;

	mtrr_type ltype;

	int i, max;

	max = num_var_ranges;

	if (replace_reg >= 0 && replace_reg < max)

		return replace_reg;

	for (i = 0; i < max; ++i) {

		mtrr_if->get(i, &lbase, &lsize, &ltype);

		if (lsize == 0)

			return i;

	}

	return -ENOSPC;

}

}

/**

 * set_fixed_ranges - checks & updates the fixed-range MTRRs if they differ from the saved set

 * set_fixed_ranges - checks & updates the fixed-range MTRRs if they

 *		      differ from the saved set

 * @frs: pointer to fixed-range MTRR values, saved by get_fixed_ranges()

 */

static int set_fixed_ranges(mtrr_type *frs)

	k8_check_syscfg_dram_mod_en();

	while (fixed_range_blocks[++block].ranges)

	while (fixed_range_blocks[++block].ranges) {

		for (range = 0; range < fixed_range_blocks[block].ranges; range++)

			set_fixed_range(fixed_range_blocks[block].base_msr + range,

					&changed, (unsigned int *)saved++);

	}

	return changed;

}

/*  Set the MSR pair relating to a var range. Returns TRUE if

    changes are made  */

/*

 * Set the MSR pair relating to a var range.

 * Returns true if changes are made.

 */

static bool set_mtrr_var_ranges(unsigned int index, struct mtrr_var_range *vr)

{

	unsigned int lo, hi;

	if ((vr->base_lo & 0xfffff0ffUL) != (lo & 0xfffff0ffUL)

	    || (vr->base_hi & (size_and_mask >> (32 - PAGE_SHIFT))) !=

		(hi & (size_and_mask >> (32 - PAGE_SHIFT)))) {

		mtrr_wrmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi);

		changed = true;

	}

 */

static unsigned long set_mtrr_state(void)

{

	unsigned int i;

	unsigned long change_mask = 0;

	unsigned int i;

	for (i = 0; i < num_var_ranges; i++)

	for (i = 0; i < num_var_ranges; i++) {

		if (set_mtrr_var_ranges(i, &mtrr_state.var_ranges[i]))

			change_mask |= MTRR_CHANGE_MASK_VARIABLE;

	}

	if (mtrr_state.have_fixed && set_fixed_ranges(mtrr_state.fixed_ranges))

		change_mask |= MTRR_CHANGE_MASK_FIXED;

	/*  Set_mtrr_restore restores the old value of MTRRdefType,

	   so to set it we fiddle with the saved value  */

	/*

	 * Set_mtrr_restore restores the old value of MTRRdefType,

	 * so to set it we fiddle with the saved value:

	 */

	if ((deftype_lo & 0xff) != mtrr_state.def_type

	    || ((deftype_lo & 0xc00) >> 10) != mtrr_state.enabled) {

		deftype_lo = (deftype_lo & ~0xcff) | mtrr_state.def_type | (mtrr_state.enabled << 10);

		deftype_lo = (deftype_lo & ~0xcff) | mtrr_state.def_type |

			     (mtrr_state.enabled << 10);

		change_mask |= MTRR_CHANGE_MASK_DEFTYPE;

	}

}

static unsigned long cr4 = 0;

static unsigned long cr4;

static DEFINE_SPINLOCK(set_atomicity_lock);

/*

 * Since we are disabling the cache don't allow any interrupts - they

 * would run extremely slow and would only increase the pain.  The caller must

 * ensure that local interrupts are disabled and are reenabled after post_set()

 * has been called.

 * Since we are disabling the cache don't allow any interrupts,

 * they would run extremely slow and would only increase the pain.

 *

 * The caller must ensure that local interrupts are disabled and

 * are reenabled after post_set() has been called.

 */

static void prepare_set(void) __acquires(set_atomicity_lock)

{

	unsigned long cr0;

	/*  Note that this is not ideal, since the cache is only flushed/disabled

	   for this CPU while the MTRRs are changed, but changing this requires

	   more invasive changes to the way the kernel boots  */

	/*

	 * Note that this is not ideal

	 * since the cache is only flushed/disabled for this CPU while the

	 * MTRRs are changed, but changing this requires more invasive

	 * changes to the way the kernel boots

	 */

	spin_lock(&set_atomicity_lock);

}

/**

 * generic_set_mtrr - set variable MTRR register on the local CPU.

 *

 * @reg: The register to set.

 * @base: The base address of the region.

 * @size: The size of the region. If this is 0 the region is disabled.

 * @type: The type of the region.

 *

 * Returns nothing.

 */

static void generic_set_mtrr(unsigned int reg, unsigned long base,

			     unsigned long size, mtrr_type type)

/*  [SUMMARY] Set variable MTRR register on the local CPU.

    <reg> The register to set.

    <base> The base address of the region.

    <size> The size of the region. If this is 0 the region is disabled.

    <type> The type of the region.

    [RETURNS] Nothing.

*/

{

	unsigned long flags;

	struct mtrr_var_range *vr;

	prepare_set();

	if (size == 0) {

		/* The invalid bit is kept in the mask, so we simply clear the

		   relevant mask register to disable a range. */

		/*

		 * The invalid bit is kept in the mask, so we simply

		 * clear the relevant mask register to disable a range.

		 */

		mtrr_wrmsr(MTRRphysMask_MSR(reg), 0, 0);

		memset(vr, 0, sizeof(struct mtrr_var_range));

	} else {

	local_irq_restore(flags);

}

int generic_validate_add_page(unsigned long base, unsigned long size, unsigned int type)

int generic_validate_add_page(unsigned long base, unsigned long size,

			      unsigned int type)

{

	unsigned long lbase, last;

	/*  For Intel PPro stepping <= 7, must be 4 MiB aligned 

	    and not touch 0x70000000->0x7003FFFF */

	/*

	 * For Intel PPro stepping <= 7

	 * must be 4 MiB aligned and not touch 0x70000000 -> 0x7003FFFF

	 */

	if (is_cpu(INTEL) && boot_cpu_data.x86 == 6 &&

	    boot_cpu_data.x86_model == 1 &&

	    boot_cpu_data.x86_mask <= 7) {

		if (base & ((1 << (22 - PAGE_SHIFT)) - 1)) {

			printk(KERN_WARNING "mtrr: base(0x%lx000) is not 4 MiB aligned\n", base);

			pr_warning("mtrr: base(0x%lx000) is not 4 MiB aligned\n", base);

			return -EINVAL;

		}

		if (!(base + size < 0x70000 || base > 0x7003F) &&

		    (type == MTRR_TYPE_WRCOMB

		     || type == MTRR_TYPE_WRBACK)) {

			printk(KERN_WARNING "mtrr: writable mtrr between 0x70000000 and 0x7003FFFF may hang the CPU.\n");

			pr_warning("mtrr: writable mtrr between 0x70000000 and 0x7003FFFF may hang the CPU.\n");

			return -EINVAL;

		}

	}

	/*  Check upper bits of base and last are equal and lower bits are 0

	    for base and 1 for last  */

	/*

	 * Check upper bits of base and last are equal and lower bits are 0

	 * for base and 1 for last

	 */

	last = base + size - 1;

	for (lbase = base; !(lbase & 1) && (last & 1);

	     lbase = lbase >> 1, last = last >> 1) ;

	     lbase = lbase >> 1, last = last >> 1)

		;

	if (lbase != last) {

		printk(KERN_WARNING "mtrr: base(0x%lx000) is not aligned on a size(0x%lx000) boundary\n",

		       base, size);

		pr_warning("mtrr: base(0x%lx000) is not aligned on a size(0x%lx000) boundary\n", base, size);

		return -EINVAL;

	}

	return 0;

}

static int generic_have_wrcomb(void)

{

	unsigned long config, dummy;

	rdmsr(MSR_MTRRcap, config, dummy);

	return (config & (1 << 10));

	return config & (1 << 10);

}

int positive_have_wrcomb(void)

	return 1;

}

/* generic structure...

/*

 * Generic structure...

 */

struct mtrr_ops generic_mtrr_ops = {

	.use_intel_if		= 1,