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Commit a12ebe16 authored by Vineet Gupta's avatar Vineet Gupta
Browse files

ARCv2: [nsim*hs*] Support simulation platforms for HS38x cores 



Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: default avatarVineet Gupta <vgupta@synopsys.com>
parent 65bfbcdf

arch/arc/boot/dts/nsim_hs.dts

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/*

 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 */

/dts-v1/;



/include/ "skeleton.dtsi"



/ {

	compatible = "snps,nsim_hs";

	interrupt-parent = <&core_intc>;



	chosen {

		bootargs = "earlycon=arc_uart,mmio32,0xc0fc1000,115200n8 console=ttyARC0,115200n8";

	};



	aliases {

		serial0 = &arcuart0;

	};



	fpga {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <1>;



		/* child and parent address space 1:1 mapped */

		ranges;



		core_intc: core-interrupt-controller {

			compatible = "snps,archs-intc";

			interrupt-controller;

			#interrupt-cells = <1>;

		};



		arcuart0: serial@c0fc1000 {

			compatible = "snps,arc-uart";

			reg = <0xc0fc1000 0x100>;

			interrupts = <24>;

			clock-frequency = <80000000>;

			current-speed = <115200>;

			status = "okay";

		};



		arcpct0: pct {

			compatible = "snps,archs-pct";

			#interrupt-cells = <1>;

			interrupts = <20>;

		};

	};

};

arch/arc/boot/dts/nsim_hs_idu.dts

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/*

 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 */

/dts-v1/;



/include/ "skeleton.dtsi"



/ {

	compatible = "snps,nsim_hs";

	interrupt-parent = <&core_intc>;



	chosen {

		bootargs = "earlycon=arc_uart,mmio32,0xc0fc1000,115200n8 console=ttyARC0,115200n8";

	};



	aliases {

		serial0 = &arcuart0;

	};



	fpga {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <1>;



		/* child and parent address space 1:1 mapped */

		ranges;



		core_intc: core-interrupt-controller {

			compatible = "snps,archs-intc";

			interrupt-controller;

			#interrupt-cells = <1>;

		};



		idu_intc: idu-interrupt-controller {

			compatible = "snps,archs-idu-intc";

			interrupt-controller;

			interrupt-parent = <&core_intc>;



			/*

			 * <hwirq  distribution>

			 * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3

			 */

			#interrupt-cells = <2>;



			/*

			 * upstream irqs to core intc - downstream these are

			 * "COMMON" irq 0,1..

			 */

			interrupts = <24 25 26 27 28 29 30 31>;

		};



		arcuart0: serial@c0fc1000 {

			compatible = "snps,arc-uart";

			reg = <0xc0fc1000 0x100>;

			interrupt-parent = <&idu_intc>;

			interrupts = <0 0>;

			clock-frequency = <80000000>;

			current-speed = <115200>;

			status = "okay";

		};



		arcpct0: pct {

			compatible = "snps,archs-pct";

			#interrupt-cells = <1>;

			interrupts = <20>;

		};

	};

};

arch/arc/boot/dts/nsimosci_hs.dts

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/*

 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 */

/dts-v1/;



/include/ "skeleton.dtsi"



/ {

	compatible = "snps,nsimosci_hs";

	clock-frequency = <20000000>;	/* 20 MHZ */

	#address-cells = <1>;

	#size-cells = <1>;

	interrupt-parent = <&core_intc>;



	chosen {

		/* this is for console on PGU */

		/* bootargs = "console=tty0 consoleblank=0"; */

		/* this is for console on serial */

		bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblank=0 debug";

	};



	aliases {

		serial0 = &uart0;

	};



	fpga {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <1>;



		/* child and parent address space 1:1 mapped */

		ranges;



		core_intc: core-interrupt-controller {

			compatible = "snps,archs-intc";

			interrupt-controller;

			#interrupt-cells = <1>;

		};



		uart0: serial@f0000000 {

			compatible = "ns8250";

			reg = <0xf0000000 0x2000>;

			interrupts = <24>;

			clock-frequency = <3686400>;

			baud = <115200>;

			reg-shift = <2>;

			reg-io-width = <4>;

			no-loopback-test = <1>;

		};



		pgu0: pgu@f9000000 {

			compatible = "snps,arcpgufb";

			reg = <0xf9000000 0x400>;

		};



		ps2: ps2@f9001000 {

			compatible = "snps,arc_ps2";

			reg = <0xf9000400 0x14>;

			interrupts = <27>;

			interrupt-names = "arc_ps2_irq";

		};



		eth0: ethernet@f0003000 {

			compatible = "snps,oscilan";

			reg = <0xf0003000 0x44>;

			interrupts = <25>, <26>;

			interrupt-names = "rx", "tx";

		};



		arcpct0: pct {

			compatible = "snps,archs-pct";

			#interrupt-cells = <1>;

			interrupts = <20>;

		};

	};

};

arch/arc/boot/dts/nsimosci_hs_idu.dts

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Original line number Original line Diff line number Diff line 
/*

 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 */

/dts-v1/;



/include/ "skeleton.dtsi"



/ {

	compatible = "snps,nsimosci_hs";

	clock-frequency = <5000000>;	/* 5 MHZ */

	#address-cells = <1>;

	#size-cells = <1>;

	interrupt-parent = <&core_intc>;



	chosen {

		/* this is for console on serial */

		bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblan=0 debug";

	};



	aliases {

		serial0 = &uart0;

	};



	fpga {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <1>;



		/* child and parent address space 1:1 mapped */

		ranges;



		core_intc: core-interrupt-controller {

			compatible = "snps,archs-intc";

			interrupt-controller;

			#interrupt-cells = <1>;

/*			interrupts = <16 17 18 19 20 21 22 23 24 25>; */

		};



		idu_intc: idu-interrupt-controller {

			compatible = "snps,archs-idu-intc";

			interrupt-controller;

			interrupt-parent = <&core_intc>;



			/*

			 * <hwirq  distribution>

			 * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3

			 */

			#interrupt-cells = <2>;



			/*

			 * upstream irqs to core intc - downstream these are

			 * "COMMON" irq 0,1..

			 */

			interrupts = <24 25 26 27 28 29 30 31>;

		};



		uart0: serial@f0000000 {

			compatible = "ns8250";

			reg = <0xf0000000 0x2000>;

			interrupt-parent = <&idu_intc>;

			interrupts = <0 0>; /* cmn irq 0 -> cpu irq 24

						RR distribute to all cpus */

			clock-frequency = <3686400>;

			baud = <115200>;

			reg-shift = <2>;

			reg-io-width = <4>;

			no-loopback-test = <1>;

		};



		pgu0: pgu@f9000000 {

			compatible = "snps,arcpgufb";

			reg = <0xf9000000 0x400>;

		};



		ps2: ps2@f9001000 {

			compatible = "snps,arc_ps2";

			reg = <0xf9000400 0x14>;

			interrupts = <3 0>;

			interrupt-parent = <&idu_intc>;

			interrupt-names = "arc_ps2_irq";

		};



		eth0: ethernet@f0003000 {

			compatible = "snps,oscilan";

			reg = <0xf0003000 0x44>;

			interrupt-parent = <&idu_intc>;

			interrupts = <1 2>, <2 2>;

			interrupt-names = "rx", "tx";

		};



		arcpct0: pct {

			compatible = "snps,archs-pct";

			#interrupt-cells = <1>;

			interrupts = <20>;

		};

	};

};

arch/arc/configs/nsim_hs_defconfig

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CONFIG_CROSS_COMPILE="arc-linux-uclibc-"

# CONFIG_LOCALVERSION_AUTO is not set

CONFIG_DEFAULT_HOSTNAME="ARCLinux"

# CONFIG_SWAP is not set

CONFIG_SYSVIPC=y

CONFIG_POSIX_MQUEUE=y

# CONFIG_CROSS_MEMORY_ATTACH is not set

CONFIG_HIGH_RES_TIMERS=y

CONFIG_IKCONFIG=y

CONFIG_IKCONFIG_PROC=y

CONFIG_NAMESPACES=y

# CONFIG_UTS_NS is not set

# CONFIG_PID_NS is not set

CONFIG_BLK_DEV_INITRD=y

CONFIG_INITRAMFS_SOURCE="../arc_initramfs_hs/"

CONFIG_KALLSYMS_ALL=y

CONFIG_EMBEDDED=y

# CONFIG_SLUB_DEBUG is not set

# CONFIG_COMPAT_BRK is not set

CONFIG_KPROBES=y

CONFIG_MODULES=y

# CONFIG_LBDAF is not set

# CONFIG_BLK_DEV_BSG is not set

# CONFIG_IOSCHED_DEADLINE is not set

# CONFIG_IOSCHED_CFQ is not set

CONFIG_ARC_PLAT_SIM=y

CONFIG_ISA_ARCV2=y

CONFIG_ARC_BUILTIN_DTB_NAME="nsim_hs"

CONFIG_PREEMPT=y

# CONFIG_COMPACTION is not set

CONFIG_NET=y

CONFIG_PACKET=y

CONFIG_UNIX=y

CONFIG_UNIX_DIAG=y

CONFIG_NET_KEY=y

CONFIG_INET=y

# CONFIG_IPV6 is not set

# CONFIG_STANDALONE is not set

# CONFIG_PREVENT_FIRMWARE_BUILD is not set

# CONFIG_FIRMWARE_IN_KERNEL is not set

# CONFIG_BLK_DEV is not set

# CONFIG_INPUT_MOUSEDEV_PSAUX is not set

# CONFIG_INPUT_KEYBOARD is not set

# CONFIG_INPUT_MOUSE is not set

# CONFIG_SERIO is not set

# CONFIG_LEGACY_PTYS is not set

# CONFIG_DEVKMEM is not set

CONFIG_SERIAL_ARC=y

CONFIG_SERIAL_ARC_CONSOLE=y

# CONFIG_HW_RANDOM is not set

# CONFIG_HWMON is not set

# CONFIG_VGA_CONSOLE is not set

# CONFIG_HID is not set

# CONFIG_USB_SUPPORT is not set

# CONFIG_IOMMU_SUPPORT is not set

CONFIG_EXT2_FS=y

CONFIG_EXT2_FS_XATTR=y

CONFIG_TMPFS=y

# CONFIG_MISC_FILESYSTEMS is not set

CONFIG_NFS_FS=y

# CONFIG_ENABLE_WARN_DEPRECATED is not set

# CONFIG_ENABLE_MUST_CHECK is not set

# CONFIG_DEBUG_PREEMPT is not set

CONFIG_XZ_DEC=y