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Commit a11a2f8f authored by Tomasz Figa's avatar Tomasz Figa Committed by Mike Turquette
Browse files

clk: samsung: exynos4: Remove unused static clkdev aliases 



Since Exynos does not support legacy non-DT boot anymore, most of clock
lookups happen using device tree, so most of static clkdev aliases are no
longer necessary. This patch removes them.

Signed-off-by: default avatarTomasz Figa <t.figa@samsung.com>
Signed-off-by: default avatarKyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: default avatarSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
parent 3a647895

drivers/clk/samsung/clk-exynos4.c

+172 −184
Original line number Diff line number Diff line
@@ -374,7 +374,7 @@ static struct samsung_mux_clock exynos4_mux_clks[] __initdata = { 
			CLK_SET_RATE_PARENT, 0),

	MUX(none, "mout_spdif", mout_spdif_p, SRC_PERIL1, 8, 2),

	MUX(none, "mout_onenand1", mout_onenand1_p, SRC_TOP0, 0, 1),

	MUX_A(sclk_epll, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1, "sclk_epll"),

	MUX(sclk_epll, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1),

	MUX(none, "mout_onenand", mout_onenand_p, SRC_TOP0, 28, 1),

};
@@ -394,8 +394,7 @@ static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = { 
	MUX(none, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4),

	MUX(sclk_mpll, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1),

	MUX(mout_core, "mout_core", mout_core_p4210, SRC_CPU, 16, 1),

	MUX_A(sclk_vpll, "sclk_vpll", sclk_vpll_p4210,

			SRC_TOP0, 8, 1, "sclk_vpll"),

	MUX(sclk_vpll, "sclk_vpll", sclk_vpll_p4210, SRC_TOP0, 8, 1),

	MUX(mout_fimc0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4),

	MUX(mout_fimc1, "mout_fimc1", group1_p4210, SRC_CAM, 4, 4),

	MUX(mout_fimc2, "mout_fimc2", group1_p4210, SRC_CAM, 8, 4),
@@ -451,10 +450,8 @@ static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = { 
	MUX(none, "mout_jpeg0", sclk_ampll_p4x12, E4X12_SRC_CAM1, 0, 1),

	MUX(none, "mout_jpeg1", sclk_evpll_p, E4X12_SRC_CAM1, 4, 1),

	MUX(none, "mout_jpeg", mout_jpeg_p, E4X12_SRC_CAM1, 8, 1),

	MUX_A(sclk_mpll, "sclk_mpll", mout_mpll_p,

			SRC_DMC, 12, 1, "sclk_mpll"),

	MUX_A(sclk_vpll, "sclk_vpll", mout_vpll_p,

			SRC_TOP0, 8, 1, "sclk_vpll"),

	MUX(sclk_mpll, "sclk_mpll", mout_mpll_p, SRC_DMC, 12, 1),

	MUX(sclk_vpll, "sclk_vpll", mout_vpll_p, SRC_TOP0, 8, 1),

	MUX(mout_core, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1),

	MUX(mout_fimc0, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4),

	MUX(mout_fimc1, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4),
@@ -544,8 +541,7 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = { 
	DIV(none, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4),

	DIV(none, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4),

	DIV(arm_clk, "arm_clk", "div_core2", DIV_CPU0, 28, 3),

	DIV_A(sclk_apll, "sclk_apll", "mout_apll",

			DIV_CPU0, 24, 3, "sclk_apll"),

	DIV(sclk_apll, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),

	DIV_F(none, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4,

			CLK_SET_RATE_PARENT, 0),

	DIV_F(none, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8,
@@ -630,160 +626,147 @@ static struct samsung_gate_clock exynos4_gate_clks[] __initdata = { 
			CLK_SET_RATE_PARENT, 0),

	GATE(sclk_audio1, "sclk_audio1", "div_audio1", SRC_MASK_PERIL1, 0,

			CLK_SET_RATE_PARENT, 0),

	GATE_D(vp, "s5p-mixer", "vp", "aclk160", GATE_IP_TV, 0, 0, 0),

	GATE_D(mixer, "s5p-mixer", "mixer", "aclk160", GATE_IP_TV, 1, 0, 0),

	GATE_D(hdmi, "exynos4-hdmi", "hdmi", "aclk160", GATE_IP_TV, 3, 0, 0),

	GATE_A(pwm, "pwm", "aclk100", GATE_IP_PERIL, 24, 0, 0, "timers"),

	GATE_A(sdmmc4, "sdmmc4", "aclk133", GATE_IP_FSYS, 9, 0, 0, "biu"),

	GATE_A(usb_host, "usb_host", "aclk133",

			GATE_IP_FSYS, 12, 0, 0, "usbhost"),

	GATE_DA(sclk_fimc0, "exynos4-fimc.0", "sclk_fimc0", "div_fimc0",

			SRC_MASK_CAM, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimc"),

	GATE_DA(sclk_fimc1, "exynos4-fimc.1", "sclk_fimc1", "div_fimc1",

			SRC_MASK_CAM, 4, CLK_SET_RATE_PARENT, 0, "sclk_fimc"),

	GATE_DA(sclk_fimc2, "exynos4-fimc.2", "sclk_fimc2", "div_fimc2",

			SRC_MASK_CAM, 8, CLK_SET_RATE_PARENT, 0, "sclk_fimc"),

	GATE_DA(sclk_fimc3, "exynos4-fimc.3", "sclk_fimc3", "div_fimc3",

			SRC_MASK_CAM, 12, CLK_SET_RATE_PARENT, 0, "sclk_fimc"),

	GATE_DA(sclk_csis0, "s5p-mipi-csis.0", "sclk_csis0", "div_csis0",

			SRC_MASK_CAM, 24, CLK_SET_RATE_PARENT, 0, "sclk_csis"),

	GATE_DA(sclk_csis1, "s5p-mipi-csis.1", "sclk_csis1", "div_csis1",

			SRC_MASK_CAM, 28, CLK_SET_RATE_PARENT, 0, "sclk_csis"),

	GATE_DA(sclk_fimd0, "exynos4-fb.0", "sclk_fimd0", "div_fimd0",

			SRC_MASK_LCD0, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimd"),

	GATE_DA(sclk_mmc0, "exynos4-sdhci.0", "sclk_mmc0", "div_mmc_pre0",

			SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0,

			"mmc_busclk.2"),

	GATE_DA(sclk_mmc1, "exynos4-sdhci.1", "sclk_mmc1", "div_mmc_pre1",

			SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0,

			"mmc_busclk.2"),

	GATE_DA(sclk_mmc2, "exynos4-sdhci.2", "sclk_mmc2", "div_mmc_pre2",

			SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0,

			"mmc_busclk.2"),

	GATE_DA(sclk_mmc3, "exynos4-sdhci.3", "sclk_mmc3", "div_mmc_pre3",

			SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0,

			"mmc_busclk.2"),

	GATE_DA(sclk_mmc4, NULL, "sclk_mmc4", "div_mmc_pre4",

			SRC_MASK_FSYS, 16, CLK_SET_RATE_PARENT, 0, "ciu"),

	GATE_DA(sclk_uart0, "exynos4210-uart.0", "uclk0", "div_uart0",

			SRC_MASK_PERIL0, 0, CLK_SET_RATE_PARENT,

			0, "clk_uart_baud0"),

	GATE_DA(sclk_uart1, "exynos4210-uart.1", "uclk1", "div_uart1",

			SRC_MASK_PERIL0, 4, CLK_SET_RATE_PARENT,

			0, "clk_uart_baud0"),

	GATE_DA(sclk_uart2, "exynos4210-uart.2", "uclk2", "div_uart2",

			SRC_MASK_PERIL0, 8, CLK_SET_RATE_PARENT,

			0, "clk_uart_baud0"),

	GATE_DA(sclk_uart3, "exynos4210-uart.3", "uclk3", "div_uart3",

			SRC_MASK_PERIL0, 12, CLK_SET_RATE_PARENT,

			0, "clk_uart_baud0"),

	GATE_DA(sclk_uart4, "exynos4210-uart.4", "uclk4", "div_uart4",

			SRC_MASK_PERIL0, 16, CLK_SET_RATE_PARENT,

			0, "clk_uart_baud0"),

	GATE(vp, "vp", "aclk160", GATE_IP_TV, 0, 0, 0),

	GATE(mixer, "mixer", "aclk160", GATE_IP_TV, 1, 0, 0),

	GATE(hdmi, "hdmi", "aclk160", GATE_IP_TV, 3, 0, 0),

	GATE(pwm, "pwm", "aclk100", GATE_IP_PERIL, 24, 0, 0),

	GATE(sdmmc4, "sdmmc4", "aclk133", GATE_IP_FSYS, 9, 0, 0),

	GATE(usb_host, "usb_host", "aclk133", GATE_IP_FSYS, 12, 0, 0),

	GATE(sclk_fimc0, "sclk_fimc0", "div_fimc0", SRC_MASK_CAM, 0,

			CLK_SET_RATE_PARENT, 0),

	GATE(sclk_fimc1, "sclk_fimc1", "div_fimc1", SRC_MASK_CAM, 4,

			CLK_SET_RATE_PARENT, 0),

	GATE(sclk_fimc2, "sclk_fimc2", "div_fimc2", SRC_MASK_CAM, 8,

			CLK_SET_RATE_PARENT, 0),

	GATE(sclk_fimc3, "sclk_fimc3", "div_fimc3", SRC_MASK_CAM, 12,

			CLK_SET_RATE_PARENT, 0),

	GATE(sclk_csis0, "sclk_csis0", "div_csis0", SRC_MASK_CAM, 24,

			CLK_SET_RATE_PARENT, 0),

	GATE(sclk_csis1, "sclk_csis1", "div_csis1", SRC_MASK_CAM, 28,

			CLK_SET_RATE_PARENT, 0),

	GATE(sclk_fimd0, "sclk_fimd0", "div_fimd0", SRC_MASK_LCD0, 0,

			CLK_SET_RATE_PARENT, 0),

	GATE(sclk_mmc0, "sclk_mmc0", "div_mmc_pre0", SRC_MASK_FSYS, 0,

			CLK_SET_RATE_PARENT, 0),

	GATE(sclk_mmc1, "sclk_mmc1", "div_mmc_pre1", SRC_MASK_FSYS, 4,

			CLK_SET_RATE_PARENT, 0),

	GATE(sclk_mmc2, "sclk_mmc2", "div_mmc_pre2", SRC_MASK_FSYS, 8,

			CLK_SET_RATE_PARENT, 0),

	GATE(sclk_mmc3, "sclk_mmc3", "div_mmc_pre3", SRC_MASK_FSYS, 12,

			CLK_SET_RATE_PARENT, 0),

	GATE(sclk_mmc4, "sclk_mmc4", "div_mmc_pre4", SRC_MASK_FSYS, 16,

			CLK_SET_RATE_PARENT, 0),

	GATE(sclk_uart0, "uclk0", "div_uart0", SRC_MASK_PERIL0, 0,

			CLK_SET_RATE_PARENT, 0),

	GATE(sclk_uart1, "uclk1", "div_uart1", SRC_MASK_PERIL0, 4,

			CLK_SET_RATE_PARENT, 0),

	GATE(sclk_uart2, "uclk2", "div_uart2", SRC_MASK_PERIL0, 8,

			CLK_SET_RATE_PARENT, 0),

	GATE(sclk_uart3, "uclk3", "div_uart3", SRC_MASK_PERIL0, 12,

			CLK_SET_RATE_PARENT, 0),

	GATE(sclk_uart4, "uclk4", "div_uart4", SRC_MASK_PERIL0, 16,

			CLK_SET_RATE_PARENT, 0),

	GATE(sclk_audio2, "sclk_audio2", "div_audio2", SRC_MASK_PERIL1, 4,

			CLK_SET_RATE_PARENT, 0),

	GATE_DA(sclk_spi0, "exynos4210-spi.0", "sclk_spi0", "div_spi_pre0",

			SRC_MASK_PERIL1, 16, CLK_SET_RATE_PARENT,

			0, "spi_busclk0"),

	GATE_DA(sclk_spi1, "exynos4210-spi.1", "sclk_spi1", "div_spi_pre1",

			SRC_MASK_PERIL1, 20, CLK_SET_RATE_PARENT,

			0, "spi_busclk0"),

	GATE_DA(sclk_spi2, "exynos4210-spi.2", "sclk_spi2", "div_spi_pre2",

			SRC_MASK_PERIL1, 24, CLK_SET_RATE_PARENT,

			0, "spi_busclk0"),

	GATE_DA(fimc0, "exynos4-fimc.0", "fimc0", "aclk160",

			GATE_IP_CAM, 0, 0, 0, "fimc"),

	GATE_DA(fimc1, "exynos4-fimc.1", "fimc1", "aclk160",

			GATE_IP_CAM, 1, 0, 0, "fimc"),

	GATE_DA(fimc2, "exynos4-fimc.2", "fimc2", "aclk160",

			GATE_IP_CAM, 2, 0, 0, "fimc"),

	GATE_DA(fimc3, "exynos4-fimc.3", "fimc3", "aclk160",

			GATE_IP_CAM, 3, 0, 0, "fimc"),

	GATE_DA(csis0, "s5p-mipi-csis.0", "csis0", "aclk160",

			GATE_IP_CAM, 4, 0, 0, "fimc"),

	GATE_DA(csis1, "s5p-mipi-csis.1", "csis1", "aclk160",

			GATE_IP_CAM, 5, 0, 0, "fimc"),

	GATE_DA(smmu_fimc0, "exynos-sysmmu.5", "smmu_fimc0", "aclk160",

			GATE_IP_CAM, 7, 0, 0, "sysmmu"),

	GATE_DA(smmu_fimc1, "exynos-sysmmu.6", "smmu_fimc1", "aclk160",

			GATE_IP_CAM, 8, 0, 0, "sysmmu"),

	GATE_DA(smmu_fimc2, "exynos-sysmmu.7", "smmu_fimc2", "aclk160",

			GATE_IP_CAM, 9, 0, 0, "sysmmu"),

	GATE_DA(smmu_fimc3, "exynos-sysmmu.8", "smmu_fimc3", "aclk160",

			GATE_IP_CAM, 10, 0, 0, "sysmmu"),

	GATE_DA(smmu_jpeg, "exynos-sysmmu.3", "smmu_jpeg", "aclk160",

			GATE_IP_CAM, 11, 0, 0, "sysmmu"),

	GATE(sclk_spi0, "sclk_spi0", "div_spi_pre0", SRC_MASK_PERIL1, 16,

			CLK_SET_RATE_PARENT, 0),

	GATE(sclk_spi1, "sclk_spi1", "div_spi_pre1", SRC_MASK_PERIL1, 20,

			CLK_SET_RATE_PARENT, 0),

	GATE(sclk_spi2, "sclk_spi2", "div_spi_pre2", SRC_MASK_PERIL1, 24,

			CLK_SET_RATE_PARENT, 0),

	GATE(fimc0, "fimc0", "aclk160", GATE_IP_CAM, 0,

			0, 0),

	GATE(fimc1, "fimc1", "aclk160", GATE_IP_CAM, 1,

			0, 0),

	GATE(fimc2, "fimc2", "aclk160", GATE_IP_CAM, 2,

			0, 0),

	GATE(fimc3, "fimc3", "aclk160", GATE_IP_CAM, 3,

			0, 0),

	GATE(csis0, "csis0", "aclk160", GATE_IP_CAM, 4,

			0, 0),

	GATE(csis1, "csis1", "aclk160", GATE_IP_CAM, 5,

			0, 0),

	GATE(smmu_fimc0, "smmu_fimc0", "aclk160", GATE_IP_CAM, 7,

			0, 0),

	GATE(smmu_fimc1, "smmu_fimc1", "aclk160", GATE_IP_CAM, 8,

			0, 0),

	GATE(smmu_fimc2, "smmu_fimc2", "aclk160", GATE_IP_CAM, 9,

			0, 0),

	GATE(smmu_fimc3, "smmu_fimc3", "aclk160", GATE_IP_CAM, 10,

			0, 0),

	GATE(smmu_jpeg, "smmu_jpeg", "aclk160", GATE_IP_CAM, 11,

			0, 0),

	GATE(pixelasyncm0, "pxl_async0", "aclk160", GATE_IP_CAM, 17, 0, 0),

	GATE(pixelasyncm1, "pxl_async1", "aclk160", GATE_IP_CAM, 18, 0, 0),

	GATE_DA(smmu_tv, "exynos-sysmmu.2", "smmu_tv", "aclk160",

			GATE_IP_TV, 4, 0, 0, "sysmmu"),

	GATE_DA(mfc, "s5p-mfc", "mfc", "aclk100", GATE_IP_MFC, 0, 0, 0, "mfc"),

	GATE_DA(smmu_mfcl, "exynos-sysmmu.0", "smmu_mfcl", "aclk100",

			GATE_IP_MFC, 1, 0, 0, "sysmmu"),

	GATE_DA(smmu_mfcr, "exynos-sysmmu.1", "smmu_mfcr", "aclk100",

			GATE_IP_MFC, 2, 0, 0, "sysmmu"),

	GATE_DA(fimd0, "exynos4-fb.0", "fimd0", "aclk160",

			GATE_IP_LCD0, 0, 0, 0, "fimd"),

	GATE_DA(smmu_fimd0, "exynos-sysmmu.10", "smmu_fimd0", "aclk160",

			GATE_IP_LCD0, 4, 0, 0, "sysmmu"),

	GATE_DA(pdma0, "dma-pl330.0", "pdma0", "aclk133",

			GATE_IP_FSYS, 0, 0, 0, "dma"),

	GATE_DA(pdma1, "dma-pl330.1", "pdma1", "aclk133",

			GATE_IP_FSYS, 1, 0, 0, "dma"),

	GATE_DA(sdmmc0, "exynos4-sdhci.0", "sdmmc0", "aclk133",

			GATE_IP_FSYS, 5, 0, 0, "hsmmc"),

	GATE_DA(sdmmc1, "exynos4-sdhci.1", "sdmmc1", "aclk133",

			GATE_IP_FSYS, 6, 0, 0, "hsmmc"),

	GATE_DA(sdmmc2, "exynos4-sdhci.2", "sdmmc2", "aclk133",

			GATE_IP_FSYS, 7, 0, 0, "hsmmc"),

	GATE_DA(sdmmc3, "exynos4-sdhci.3", "sdmmc3", "aclk133",

			GATE_IP_FSYS, 8, 0, 0, "hsmmc"),

	GATE_DA(uart0, "exynos4210-uart.0", "uart0", "aclk100",

			GATE_IP_PERIL, 0, 0, 0, "uart"),

	GATE_DA(uart1, "exynos4210-uart.1", "uart1", "aclk100",

			GATE_IP_PERIL, 1, 0, 0, "uart"),

	GATE_DA(uart2, "exynos4210-uart.2", "uart2", "aclk100",

			GATE_IP_PERIL, 2, 0, 0, "uart"),

	GATE_DA(uart3, "exynos4210-uart.3", "uart3", "aclk100",

			GATE_IP_PERIL, 3, 0, 0, "uart"),

	GATE_DA(uart4, "exynos4210-uart.4", "uart4", "aclk100",

			GATE_IP_PERIL, 4, 0, 0, "uart"),

	GATE_DA(i2c0, "s3c2440-i2c.0", "i2c0", "aclk100",

			GATE_IP_PERIL, 6, 0, 0, "i2c"),

	GATE_DA(i2c1, "s3c2440-i2c.1", "i2c1", "aclk100",

			GATE_IP_PERIL, 7, 0, 0, "i2c"),

	GATE_DA(i2c2, "s3c2440-i2c.2", "i2c2", "aclk100",

			GATE_IP_PERIL, 8, 0, 0, "i2c"),

	GATE_DA(i2c3, "s3c2440-i2c.3", "i2c3", "aclk100",

			GATE_IP_PERIL, 9, 0, 0, "i2c"),

	GATE_DA(i2c4, "s3c2440-i2c.4", "i2c4", "aclk100",

			GATE_IP_PERIL, 10, 0, 0, "i2c"),

	GATE_DA(i2c5, "s3c2440-i2c.5", "i2c5", "aclk100",

			GATE_IP_PERIL, 11, 0, 0, "i2c"),

	GATE_DA(i2c6, "s3c2440-i2c.6", "i2c6", "aclk100",

			GATE_IP_PERIL, 12, 0, 0, "i2c"),

	GATE_DA(i2c7, "s3c2440-i2c.7", "i2c7", "aclk100",

			GATE_IP_PERIL, 13, 0, 0, "i2c"),

	GATE_DA(i2c_hdmi, "s3c2440-hdmiphy-i2c", "i2c-hdmi", "aclk100",

			GATE_IP_PERIL, 14, 0, 0, "i2c"),

	GATE_DA(spi0, "exynos4210-spi.0", "spi0", "aclk100",

			GATE_IP_PERIL, 16, 0, 0, "spi"),

	GATE_DA(spi1, "exynos4210-spi.1", "spi1", "aclk100",

			GATE_IP_PERIL, 17, 0, 0, "spi"),

	GATE_DA(spi2, "exynos4210-spi.2", "spi2", "aclk100",

			GATE_IP_PERIL, 18, 0, 0, "spi"),

	GATE_DA(i2s1, "samsung-i2s.1", "i2s1", "aclk100",

			GATE_IP_PERIL, 20, 0, 0, "iis"),

	GATE_DA(i2s2, "samsung-i2s.2", "i2s2", "aclk100",

			GATE_IP_PERIL, 21, 0, 0, "iis"),

	GATE_DA(pcm1, "samsung-pcm.1", "pcm1", "aclk100",

			GATE_IP_PERIL, 22, 0, 0, "pcm"),

	GATE_DA(pcm2, "samsung-pcm.2", "pcm2", "aclk100",

			GATE_IP_PERIL, 23, 0, 0, "pcm"),

	GATE_DA(spdif, "samsung-spdif", "spdif", "aclk100",

			GATE_IP_PERIL, 26, 0, 0, "spdif"),

	GATE_DA(ac97, "samsung-ac97", "ac97", "aclk100",

			GATE_IP_PERIL, 27, 0, 0, "ac97"),

	GATE(smmu_tv, "smmu_tv", "aclk160", GATE_IP_TV, 4,

			0, 0),

	GATE(mfc, "mfc", "aclk100", GATE_IP_MFC, 0, 0, 0),

	GATE(smmu_mfcl, "smmu_mfcl", "aclk100", GATE_IP_MFC, 1,

			0, 0),

	GATE(smmu_mfcr, "smmu_mfcr", "aclk100", GATE_IP_MFC, 2,

			0, 0),

	GATE(fimd0, "fimd0", "aclk160", GATE_IP_LCD0, 0,

			0, 0),

	GATE(smmu_fimd0, "smmu_fimd0", "aclk160", GATE_IP_LCD0, 4,

			0, 0),

	GATE(pdma0, "pdma0", "aclk133", GATE_IP_FSYS, 0,

			0, 0),

	GATE(pdma1, "pdma1", "aclk133", GATE_IP_FSYS, 1,

			0, 0),

	GATE(sdmmc0, "sdmmc0", "aclk133", GATE_IP_FSYS, 5,

			0, 0),

	GATE(sdmmc1, "sdmmc1", "aclk133", GATE_IP_FSYS, 6,

			0, 0),

	GATE(sdmmc2, "sdmmc2", "aclk133", GATE_IP_FSYS, 7,

			0, 0),

	GATE(sdmmc3, "sdmmc3", "aclk133", GATE_IP_FSYS, 8,

			0, 0),

	GATE(uart0, "uart0", "aclk100", GATE_IP_PERIL, 0,

			0, 0),

	GATE(uart1, "uart1", "aclk100", GATE_IP_PERIL, 1,

			0, 0),

	GATE(uart2, "uart2", "aclk100", GATE_IP_PERIL, 2,

			0, 0),

	GATE(uart3, "uart3", "aclk100", GATE_IP_PERIL, 3,

			0, 0),

	GATE(uart4, "uart4", "aclk100", GATE_IP_PERIL, 4,

			0, 0),

	GATE(i2c0, "i2c0", "aclk100", GATE_IP_PERIL, 6,

			0, 0),

	GATE(i2c1, "i2c1", "aclk100", GATE_IP_PERIL, 7,

			0, 0),

	GATE(i2c2, "i2c2", "aclk100", GATE_IP_PERIL, 8,

			0, 0),

	GATE(i2c3, "i2c3", "aclk100", GATE_IP_PERIL, 9,

			0, 0),

	GATE(i2c4, "i2c4", "aclk100", GATE_IP_PERIL, 10,

			0, 0),

	GATE(i2c5, "i2c5", "aclk100", GATE_IP_PERIL, 11,

			0, 0),

	GATE(i2c6, "i2c6", "aclk100", GATE_IP_PERIL, 12,

			0, 0),

	GATE(i2c7, "i2c7", "aclk100", GATE_IP_PERIL, 13,

			0, 0),

	GATE(i2c_hdmi, "i2c-hdmi", "aclk100", GATE_IP_PERIL, 14,

			0, 0),

	GATE(spi0, "spi0", "aclk100", GATE_IP_PERIL, 16,

			0, 0),

	GATE(spi1, "spi1", "aclk100", GATE_IP_PERIL, 17,

			0, 0),

	GATE(spi2, "spi2", "aclk100", GATE_IP_PERIL, 18,

			0, 0),

	GATE(i2s1, "i2s1", "aclk100", GATE_IP_PERIL, 20,

			0, 0),

	GATE(i2s2, "i2s2", "aclk100", GATE_IP_PERIL, 21,

			0, 0),

	GATE(pcm1, "pcm1", "aclk100", GATE_IP_PERIL, 22,

			0, 0),

	GATE(pcm2, "pcm2", "aclk100", GATE_IP_PERIL, 23,

			0, 0),

	GATE(spdif, "spdif", "aclk100", GATE_IP_PERIL, 26,

			0, 0),

	GATE(ac97, "ac97", "aclk100", GATE_IP_PERIL, 27,

			0, 0),

};



/* list of gate clocks supported in exynos4210 soc */
@@ -812,13 +795,18 @@ static struct samsung_gate_clock exynos4210_gate_clks[] __initdata = { 
			SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),

	GATE(sclk_mixer, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4, 0, 0),

	GATE(sclk_dac, "sclk_dac", "mout_dac", SRC_MASK_TV, 8, 0, 0),

	GATE_A(tsadc, "tsadc", "aclk100", GATE_IP_PERIL, 15, 0, 0, "adc"),

	GATE_A(mct, "mct", "aclk100", E4210_GATE_IP_PERIR, 13, 0, 0, "mct"),

	GATE_A(wdt, "watchdog", "aclk100", E4210_GATE_IP_PERIR, 14, 0, 0, "watchdog"),

	GATE_A(rtc, "rtc", "aclk100", E4210_GATE_IP_PERIR, 15, 0, 0, "rtc"),

	GATE_A(keyif, "keyif", "aclk100", E4210_GATE_IP_PERIR, 16, 0, 0, "keypad"),

	GATE_DA(sclk_fimd1, "exynos4-fb.1", "sclk_fimd1", "div_fimd1",

			E4210_SRC_MASK_LCD1, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimd"),

	GATE(tsadc, "tsadc", "aclk100", GATE_IP_PERIL, 15,

			0, 0),

	GATE(mct, "mct", "aclk100", E4210_GATE_IP_PERIR, 13,

			0, 0),

	GATE(wdt, "watchdog", "aclk100", E4210_GATE_IP_PERIR, 14,

			0, 0),

	GATE(rtc, "rtc", "aclk100", E4210_GATE_IP_PERIR, 15,

			0, 0),

	GATE(keyif, "keyif", "aclk100", E4210_GATE_IP_PERIR, 16,

			0, 0),

	GATE(sclk_fimd1, "sclk_fimd1", "div_fimd1", E4210_SRC_MASK_LCD1, 0,

			CLK_SET_RATE_PARENT, 0),

	GATE(tmu_apbif, "tmu_apbif", "aclk100", E4210_GATE_IP_PERIR, 17, 0, 0),

};
@@ -842,10 +830,11 @@ static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = { 
			SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),

	GATE(smmu_rotator, "smmu_rotator", "aclk200",

			E4X12_GATE_IP_IMAGE, 4, 0, 0),

	GATE_A(mct, "mct", "aclk100", E4X12_GATE_IP_PERIR, 13, 0, 0, "mct"),

	GATE_A(rtc, "rtc", "aclk100", E4X12_GATE_IP_PERIR, 15, 0, 0, "rtc"),

	GATE_A(keyif, "keyif", "aclk100",

			E4X12_GATE_IP_PERIR, 16, 0, 0, "keypad"),

	GATE(mct, "mct", "aclk100", E4X12_GATE_IP_PERIR, 13,

			0, 0),

	GATE(rtc, "rtc", "aclk100", E4X12_GATE_IP_PERIR, 15,

			0, 0),

	GATE(keyif, "keyif", "aclk100", E4X12_GATE_IP_PERIR, 16, 0, 0),

	GATE(sclk_pwm_isp, "sclk_pwm_isp", "div_pwm_isp",

			E4X12_SRC_MASK_ISP, 0, CLK_SET_RATE_PARENT, 0),

	GATE(sclk_spi0_isp, "sclk_spi0_isp", "div_spi0_isp_pre",
@@ -862,12 +851,11 @@ static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = { 
			E4X12_GATE_IP_ISP, 2, 0, 0),

	GATE(uart_isp_sclk, "uart_isp_sclk", "sclk_uart_isp",

			E4X12_GATE_IP_ISP, 3, 0, 0),

	GATE_A(wdt, "watchdog", "aclk100",

			E4X12_GATE_IP_PERIR, 14, 0, 0, "watchdog"),

	GATE_DA(pcm0, "samsung-pcm.0", "pcm0", "aclk100",

			E4X12_GATE_IP_MAUDIO, 2, 0, 0, "pcm"),

	GATE_DA(i2s0, "samsung-i2s.0", "i2s0", "aclk100",

			E4X12_GATE_IP_MAUDIO, 3, 0, 0, "iis"),

	GATE(wdt, "watchdog", "aclk100", E4X12_GATE_IP_PERIR, 14, 0, 0),

	GATE(pcm0, "pcm0", "aclk100", E4X12_GATE_IP_MAUDIO, 2,

			0, 0),

	GATE(i2s0, "i2s0", "aclk100", E4X12_GATE_IP_MAUDIO, 3,

			0, 0),

	GATE(fimc_isp, "isp", "aclk200", E4X12_GATE_ISP0, 0,

			CLK_IGNORE_UNUSED, 0),

	GATE(fimc_drc, "drc", "aclk200", E4X12_GATE_ISP0, 1,
@@ -997,14 +985,14 @@ static struct of_device_id ext_clk_match[] __initdata = { 
};



static struct samsung_pll_clock exynos4_plls[nr_plls] __initdata = {

	[apll] = PLL_A(pll_35xx, fout_apll, "fout_apll", "fin_pll", APLL_LOCK,

		APLL_CON0, "fout_apll", NULL),

	[mpll] = PLL_A(pll_35xx, fout_mpll, "fout_mpll", "fin_pll",

		E4X12_MPLL_LOCK, E4X12_MPLL_CON0, "fout_mpll", NULL),

	[epll] = PLL_A(pll_36xx, fout_epll, "fout_epll", "fin_pll", EPLL_LOCK,

		EPLL_CON0, "fout_epll", NULL),

	[vpll] = PLL_A(pll_36xx, fout_vpll, "fout_vpll", "fin_pll", VPLL_LOCK,

		VPLL_CON0, "fout_vpll", NULL),

	[apll] = PLL(pll_35xx, fout_apll, "fout_apll", "fin_pll",

			APLL_LOCK, APLL_CON0, NULL),

	[mpll] = PLL(pll_35xx, fout_mpll, "fout_mpll", "fin_pll",

			E4X12_MPLL_LOCK, E4X12_MPLL_CON0, NULL),

	[epll] = PLL(pll_36xx, fout_epll, "fout_epll", "fin_pll",

			EPLL_LOCK, EPLL_CON0, NULL),

	[vpll] = PLL(pll_36xx, fout_vpll, "fout_vpll", "fin_pll",

			VPLL_LOCK, VPLL_CON0, NULL),

};



/* register exynos4 clocks */