Loading drivers/gpu/msm/a6xx_reg.h +1 −0 Original line number Diff line number Diff line Loading @@ -381,6 +381,7 @@ #define A6XX_RBBM_PERFCTR_RBBM_SEL_1 0x508 #define A6XX_RBBM_PERFCTR_RBBM_SEL_2 0x509 #define A6XX_RBBM_PERFCTR_RBBM_SEL_3 0x50A #define A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x50B #define A6XX_RBBM_ISDB_CNT 0x533 Loading drivers/gpu/msm/adreno_a6xx.c +4 −0 Original line number Diff line number Diff line Loading @@ -385,6 +385,10 @@ static void a6xx_start(struct adreno_device *adreno_dev) adreno_vbif_start(adreno_dev, a6xx_vbif_platforms, ARRAY_SIZE(a6xx_vbif_platforms)); /* Make all blocks contribute to the GPU BUSY perf counter */ kgsl_regwrite(device, A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xFFFFFFFF); /* * Set UCHE_WRITE_THRU_BASE to the UCHE_TRAP_BASE effectively * disabling L2 bypass Loading Loading
drivers/gpu/msm/a6xx_reg.h +1 −0 Original line number Diff line number Diff line Loading @@ -381,6 +381,7 @@ #define A6XX_RBBM_PERFCTR_RBBM_SEL_1 0x508 #define A6XX_RBBM_PERFCTR_RBBM_SEL_2 0x509 #define A6XX_RBBM_PERFCTR_RBBM_SEL_3 0x50A #define A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x50B #define A6XX_RBBM_ISDB_CNT 0x533 Loading
drivers/gpu/msm/adreno_a6xx.c +4 −0 Original line number Diff line number Diff line Loading @@ -385,6 +385,10 @@ static void a6xx_start(struct adreno_device *adreno_dev) adreno_vbif_start(adreno_dev, a6xx_vbif_platforms, ARRAY_SIZE(a6xx_vbif_platforms)); /* Make all blocks contribute to the GPU BUSY perf counter */ kgsl_regwrite(device, A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xFFFFFFFF); /* * Set UCHE_WRITE_THRU_BASE to the UCHE_TRAP_BASE effectively * disabling L2 bypass Loading