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Commit 9ff3ca58 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'edac_for_4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp 

Pull EDAC updates from Borislav Petkov:
 "A bunch of fixes all over the place and some hw enablement this time.

   - Convert EDAC to debugfs wrappers and make drivers use those
     (Borislav Petkov)

   - L3 and SoC support for xgene_edac (Loc Ho)

   - AMD F15h, models 0x60-6f support to amd64_edac (Aravind
     Gopalakrishnan)

   - Fixes and cleanups all over the place"

* tag 'edac_for_4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp: (22 commits)
  EDAC: Fix PAGES_TO_MiB macro misuse
  EDAC, altera: SoCFPGA EDAC should not look for ECC_CORR_EN
  EDAC: Use edac_debugfs_remove_recursive()
  EDAC, ppc4xx_edac: Fix module autoload for OF platform driver
  Documentation/EDAC: Add reference documents section for amd64_edac
  EDAC, amd64_edac: Update copyright and remove changelog
  EDAC, amd64_edac: Extend scrub rate support to F15hM60h
  EDAC: Don't allow empty DIMM labels
  EDAC: Fix sysfs dimm_label store operation
  EDAC: Fix sysfs dimm_label show operation
  arm64, EDAC: Add L3/SoC DT subnodes to the APM X-Gene SoC EDAC node
  EDAC, xgene: Add SoC support
  EDAC, xgene: Fix possible sprintf() overflow issue
  EDAC, xgene: Add L3 support
  EDAC, Documentation: Update X-Gene EDAC binding for L3/SoC subnodes
  EDAC, sb_edac: Fix TAD presence check for sbridge_mci_bind_devs()
  EDAC, ghes_edac: Remove redundant memory_type array
  EDAC, xgene: Convert to debugfs wrappers
  EDAC, i5100: Convert to debugfs wrappers
  EDAC, altera: Convert to debugfs wrappers
  ...
parents 17a13590 990995ba

Documentation/devicetree/bindings/edac/apm-xgene-edac.txt

+23 −0
Original line number Diff line number Diff line
@@ -5,6 +5,8 @@ The follow error types are supported: 


  memory controller	- Memory controller

  PMD (L1/L2)		- Processor module unit (PMD) L1/L2 cache

  L3			- L3 cache controller

  SoC			- SoC IP's such as Ethernet, SATA, and etc



The following section describes the EDAC DT node binding.
@@ -30,6 +32,17 @@ Required properties for PMD subnode: 
- reg			: First resource shall be the PMD resource.

- pmd-controller	: Instance number of the PMD controller.



Required properties for L3 subnode:

- compatible		: Shall be "apm,xgene-edac-l3" or

                          "apm,xgene-edac-l3-v2".

- reg			: First resource shall be the L3 EDAC resource.



Required properties for SoC subnode:

- compatible		: Shall be "apm,xgene-edac-soc-v1" for revision 1 or

                          "apm,xgene-edac-l3-soc" for general value reporting

                          only.

- reg			: First resource shall be the SoC EDAC resource.



Example:

	csw: csw@7e200000 {

		compatible = "apm,xgene-csw", "syscon";
@@ -76,4 +89,14 @@ Example: 
			reg = <0x0 0x7c000000 0x0 0x200000>;

			pmd-controller = <0>;

		};



		edacl3@7e600000 {

			compatible = "apm,xgene-edac-l3";

			reg = <0x0 0x7e600000 0x0 0x1000>;

		};



		edacsoc@7e930000 {

			compatible = "apm,xgene-edac-soc-v1";

			reg = <0x0 0x7e930000 0x0 0x1000>;

		};

	};

Documentation/edac.txt

+46 −0
Original line number Diff line number Diff line
@@ -744,6 +744,52 @@ exports one 
   possible that some errors could be lost. With rdimm's, they display the

   contents of the registers



AMD64_EDAC REFERENCE DOCUMENTS USED

-----------------------------------

amd64_edac module is based on the following documents

(available from http://support.amd.com/en-us/search/tech-docs):



1. Title:  BIOS and Kernel Developer's Guide for AMD Athlon 64 and AMD

	   Opteron Processors

   AMD publication #: 26094

   Revision: 3.26

   Link: http://support.amd.com/TechDocs/26094.PDF



2. Title:  BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh

	   Processors

   AMD publication #: 32559

   Revision: 3.00

   Issue Date: May 2006

   Link: http://support.amd.com/TechDocs/32559.pdf



3. Title:  BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h

	   Processors

   AMD publication #: 31116

   Revision: 3.00

   Issue Date: September 07, 2007

   Link: http://support.amd.com/TechDocs/31116.pdf



4. Title: BIOS and Kernel Developer's Guide (BKDG) for AMD Family 15h

	  Models 30h-3Fh Processors

   AMD publication #: 49125

   Revision: 3.06

   Issue Date: 2/12/2015 (latest release)

   Link: http://support.amd.com/TechDocs/49125_15h_Models_30h-3Fh_BKDG.pdf



5. Title: BIOS and Kernel Developer's Guide (BKDG) for AMD Family 15h

	  Models 60h-6Fh Processors

   AMD publication #: 50742

   Revision: 3.01

   Issue Date: 7/23/2015 (latest release)

   Link: http://support.amd.com/TechDocs/50742_15h_Models_60h-6Fh_BKDG.pdf



6. Title: BIOS and Kernel Developer's Guide (BKDG) for AMD Family 16h

	  Models 00h-0Fh Processors

   AMD publication #: 48751

   Revision: 3.03

   Issue Date: 2/23/2015 (latest release)

   Link: http://support.amd.com/TechDocs/48751_16h_bkdg.pdf



CREDITS:

========

arch/arm64/boot/dts/apm/apm-storm.dtsi

+10 −0
Original line number Diff line number Diff line
@@ -477,6 +477,16 @@ 
				reg = <0x0 0x7c600000 0x0 0x200000>;

				pmd-controller = <3>;

			};



			edacl3@7e600000 {

				compatible = "apm,xgene-edac-l3";

				reg = <0x0 0x7e600000 0x0 0x1000>;

			};



			edacsoc@7e930000 {

				compatible = "apm,xgene-edac-soc-v1";

				reg = <0x0 0x7e930000 0x0 0x1000>;

			};

		};



		pcie0: pcie@1f2b0000 {

drivers/edac/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -12,6 +12,8 @@ obj-$(CONFIG_EDAC_MM_EDAC) += edac_core.o 
edac_core-y	:= edac_mc.o edac_device.o edac_mc_sysfs.o

edac_core-y	+= edac_module.o edac_device_sysfs.o



edac_core-$(CONFIG_EDAC_DEBUG)		+= debugfs.o



ifdef CONFIG_PCI

edac_core-y	+= edac_pci.o edac_pci_sysfs.o

endif

drivers/edac/altera_edac.c

+8 −12
Original line number Diff line number Diff line
@@ -51,11 +51,9 @@ static const struct altr_sdram_prv_data c5_data = { 
	.ecc_irq_clr_mask   = (CV_DRAMINTR_INTRCLR | CV_DRAMINTR_INTREN),

	.ecc_cnt_rst_offset = CV_DRAMINTR_OFST,

	.ecc_cnt_rst_mask   = CV_DRAMINTR_INTRCLR,

#ifdef CONFIG_EDAC_DEBUG

	.ce_ue_trgr_offset  = CV_CTLCFG_OFST,

	.ce_set_mask        = CV_CTLCFG_GEN_SB_ERR,

	.ue_set_mask        = CV_CTLCFG_GEN_DB_ERR,

#endif

};



static const struct altr_sdram_prv_data a10_data = {
@@ -72,11 +70,9 @@ static const struct altr_sdram_prv_data a10_data = { 
	.ecc_irq_clr_mask   = (A10_INTSTAT_SBEERR | A10_INTSTAT_DBEERR),

	.ecc_cnt_rst_offset = A10_ECCCTRL1_OFST,

	.ecc_cnt_rst_mask   = A10_ECC_CNT_RESET_MASK,

#ifdef CONFIG_EDAC_DEBUG

	.ce_ue_trgr_offset  = A10_DIAGINTTEST_OFST,

	.ce_set_mask        = A10_DIAGINT_TSERRA_MASK,

	.ue_set_mask        = A10_DIAGINT_TDERRA_MASK,

#endif

};



static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id)
@@ -116,7 +112,6 @@ static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id) 
	return IRQ_NONE;

}



#ifdef CONFIG_EDAC_DEBUG

static ssize_t altr_sdr_mc_err_inject_write(struct file *file,

					    const char __user *data,

					    size_t count, loff_t *ppos)
@@ -191,14 +186,15 @@ static const struct file_operations altr_sdr_mc_debug_inject_fops = { 


static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci)

{

	if (mci->debugfs)

		debugfs_create_file("inject_ctrl", S_IWUSR, mci->debugfs, mci,

	if (!IS_ENABLED(CONFIG_EDAC_DEBUG))

		return;



	if (!mci->debugfs)

		return;



	edac_debugfs_create_file("inject_ctrl", S_IWUSR, mci->debugfs, mci,

				 &altr_sdr_mc_debug_inject_fops);

}

#else

static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci)

{}

#endif



/* Get total memory size from Open Firmware DTB */

static unsigned long get_total_mem(void)