Commit 9fc043e0 authored Apr 21, 2017 by Harshdeep Dhatt

msm: kgsl: Set Clear bit to 0 in CP_PROTECT_CNTL for a6xx



Currently this bit is set to 1. This causes the contents
of CP_PROTECT_STATUS to be cleared out when it is read in
CP_REGISTER_PROTECTED_ERROR interrupt. Set this bit to 0
so that CP_PROTECT_STATUS is not cleared out.

Change-Id: I8be85c1c93b303171d8ca77c086d62988b8087fc
Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>

parent fa403c81

drivers/gpu/msm/adreno_a6xx.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -125,7 +125,7 @@ static void a6xx_protect_init(struct adreno_device *adreno_dev)
		unsigned int mmu_base = 0, mmu_range = 0, cur_range;

		/* enable access protection to privileged registers */
		kgsl_regwrite(device, A6XX_CP_PROTECT_CNTL, 0x00000007);
		kgsl_regwrite(device, A6XX_CP_PROTECT_CNTL, 0x00000003);

		if (mmu_prot) {
		mmu_base = mmu_prot->base;