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Commit 9f4283f4 authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
Browse files

drm/radeon/kms: add missing frac fb div flag for dce4+ 

The fixed ref/post dividers are set by the AdjustPll table
rather than the ss info table on dce4+.  Make sure we enable
the fractional feedback dividers when using a fixed post
or ref divider on them as well.

Fixes:
https://bugzilla.kernel.org/show_bug.cgi?id=29272



Signed-off-by: default avatarAlex Deucher <alexdeucher@gmail.com>
Cc: stable@kernel.org
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 16e4b8a6

drivers/gpu/drm/radeon/atombios_crtc.c

+3 −1
Original line number Diff line number Diff line
@@ -557,9 +557,9 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, 


			/* use recommended ref_div for ss */

			if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {

				pll->flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;

				if (ss_enabled) {

					if (ss->refdiv) {

						pll->flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;

						pll->flags |= RADEON_PLL_USE_REF_DIV;

						pll->reference_div = ss->refdiv;

						if (ASIC_IS_AVIVO(rdev))
@@ -662,10 +662,12 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, 
						   index, (uint32_t *)&args);

				adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;

				if (args.v3.sOutput.ucRefDiv) {

					pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;

					pll->flags |= RADEON_PLL_USE_REF_DIV;

					pll->reference_div = args.v3.sOutput.ucRefDiv;

				}

				if (args.v3.sOutput.ucPostDiv) {

					pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;

					pll->flags |= RADEON_PLL_USE_POST_DIV;

					pll->post_div = args.v3.sOutput.ucPostDiv;

				}