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Commit 9ed35ab1 authored by Paulo Zanoni's avatar Paulo Zanoni Committed by Daniel Vetter
Browse files

drm/i915: add aux_ch_ctl_reg to struct intel_dp 



This way we can remove some duplicated code and avoid more mistakes
and regressions with these registers in the future.

Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent b90f5176

drivers/gpu/drm/i915/intel_dp.c

+21 −45
Original line number Diff line number Diff line
@@ -328,29 +328,10 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) 
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

	struct drm_device *dev = intel_dig_port->base.base.dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	uint32_t ch_ctl = intel_dp->output_reg + 0x10;

	uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;

	uint32_t status;

	bool done;



	if (HAS_DDI(dev)) {

		switch (intel_dig_port->port) {

		case PORT_A:

			ch_ctl = DPA_AUX_CH_CTL;

			break;

		case PORT_B:

			ch_ctl = PCH_DPB_AUX_CH_CTL;

			break;

		case PORT_C:

			ch_ctl = PCH_DPC_AUX_CH_CTL;

			break;

		case PORT_D:

			ch_ctl = PCH_DPD_AUX_CH_CTL;

			break;

		default:

			BUG();

		}

	}



#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)

	if (has_aux_irq)

		done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
@@ -370,11 +351,10 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, 
		uint8_t *send, int send_bytes,

		uint8_t *recv, int recv_size)

{

	uint32_t output_reg = intel_dp->output_reg;

	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

	struct drm_device *dev = intel_dig_port->base.base.dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	uint32_t ch_ctl = output_reg + 0x10;

	uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;

	uint32_t ch_data = ch_ctl + 4;

	int i, ret, recv_bytes;

	uint32_t status;
@@ -388,29 +368,6 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, 
	 */

	pm_qos_update_request(&dev_priv->pm_qos, 0);



	if (HAS_DDI(dev)) {

		switch (intel_dig_port->port) {

		case PORT_A:

			ch_ctl = DPA_AUX_CH_CTL;

			ch_data = DPA_AUX_CH_DATA1;

			break;

		case PORT_B:

			ch_ctl = PCH_DPB_AUX_CH_CTL;

			ch_data = PCH_DPB_AUX_CH_DATA1;

			break;

		case PORT_C:

			ch_ctl = PCH_DPC_AUX_CH_CTL;

			ch_data = PCH_DPC_AUX_CH_DATA1;

			break;

		case PORT_D:

			ch_ctl = PCH_DPD_AUX_CH_CTL;

			ch_data = PCH_DPD_AUX_CH_DATA1;

			break;

		default:

			BUG();

		}

	}



	intel_dp_check_edp(intel_dp);

	/* The clock divider is based off the hrawclk,

	 * and would like to run at 2MHz. So, take the
@@ -2832,6 +2789,25 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, 
	else

		intel_connector->get_hw_state = intel_connector_get_hw_state;



	intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;

	if (HAS_DDI(dev)) {

		switch (intel_dig_port->port) {

		case PORT_A:

			intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;

			break;

		case PORT_B:

			intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;

			break;

		case PORT_C:

			intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;

			break;

		case PORT_D:

			intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;

			break;

		default:

			BUG();

		}

	}



	/* Set up the DDC bus. */

	switch (port) {

drivers/gpu/drm/i915/intel_drv.h

+1 −0
Original line number Diff line number Diff line
@@ -366,6 +366,7 @@ struct intel_hdmi { 


struct intel_dp {

	uint32_t output_reg;

	uint32_t aux_ch_ctl_reg;

	uint32_t DP;

	uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];

	bool has_audio;