Revert "MIPS: Avoid pipeline stalls on some MIPS32R2 cores." (9eaffa84) · Commits · e / devices / android_kernel_fairphone_FP3

arch/mips/mm/tlbex.c

+2 −19

Original line number	Diff line number	Diff line
		@@ -512,26 +512,9 @@ static void build_tlb_write_entry(u32 p, struct uasm_label l,
		case tlb_indexed: tlbw = uasm_i_tlbwi; break;
		}

		if (cpu_has_mips_r2_exec_hazard) {
		/*
		* The architecture spec says an ehb is required here,
		* but a number of cores do not have the hazard and
		* using an ehb causes an expensive pipeline stall.
		*/
		switch (current_cpu_type()) {
		case CPU_M14KC:
		case CPU_74K:
		case CPU_1074K:
		case CPU_PROAPTIV:
		case CPU_P5600:
		case CPU_M5150:
		case CPU_QEMU_GENERIC:
		break;

		default:
		if (cpu_has_mips_r2_r6) {
		if (cpu_has_mips_r2_exec_hazard)
		uasm_i_ehb(p);
		break;
		}
		tlbw(p);
		return;
		}