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Commit 9e6f3969 authored by Shinya Kuribayashi's avatar Shinya Kuribayashi Committed by Ralf Baechle
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MIPS: EMMA2RH: Remove EMMA2RH_CPU_CASCADE 



Although all EMMAxxx SoCs can support IP2 and IP3 hardware interrupts,
current EMMA2RH plat_irq_dispatch() supports IP2 only.  We can make it
configurable in the future, but for the time being, would like to make
things explicitly allcated to IP2 in accordance with plat_irq_dispatch().

Signed-off-by: default avatarShinya Kuribayashi <shinya.kuribayashi.px@renesas.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1388/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent eebacda4

arch/mips/emma/markeins/irq.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -301,7 +301,7 @@ void __init arch_init_irq(void) 
	/* setup cascade interrupts */

	/* setup cascade interrupts */

	setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_SW_CASCADE, &irq_cascade);

	setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_SW_CASCADE, &irq_cascade);

	setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_GPIO_CASCADE, &irq_cascade);

	setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_GPIO_CASCADE, &irq_cascade);

	setup_irq(MIPS_CPU_IRQ_BASE + CPU_EMMA2RH_CASCADE, &irq_cascade);

	setup_irq(MIPS_CPU_IRQ_BASE + 2, &irq_cascade);

}

}





asmlinkage void plat_irq_dispatch(void)

asmlinkage void plat_irq_dispatch(void)

arch/mips/include/asm/emma/emma2rh.h

+0 −1
Original line number Original line Diff line number Diff line
@@ -101,7 +101,6 @@ 




#define NUM_EMMA2RH_IRQ		96

#define NUM_EMMA2RH_IRQ		96





#define CPU_EMMA2RH_CASCADE	2

#define EMMA2RH_IRQ_BASE	(MIPS_CPU_IRQ_BASE + 8)

#define EMMA2RH_IRQ_BASE	(MIPS_CPU_IRQ_BASE + 8)





/*

/*