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Commit 9e5acbc2 authored by Denys Vlasenko's avatar Denys Vlasenko Committed by Alex Deucher
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radeon: Deinline indirect register accessor functions 

This patch deinlines indirect register accessor functions.

These functions perform two mmio accesses, framed by spin lock/unlock.
Spin lock/unlock by itself takes more than 50 cycles in ideal case
(if lock is exclusively cached on current CPU).

With this .config: http://busybox.net/~vda/kernel_config

,
after uninlining these functions have sizes and callsite counts
as follows:

r600_uvd_ctx_rreg: 111 bytes, 4 callsites
r600_uvd_ctx_wreg: 113 bytes, 5 callsites
eg_pif_phy0_rreg: 106 bytes, 13 callsites
eg_pif_phy0_wreg: 108 bytes, 13 callsites
eg_pif_phy1_rreg: 107 bytes, 13 callsites
eg_pif_phy1_wreg: 108 bytes, 13 callsites
rv370_pcie_rreg: 111 bytes, 21 callsites
rv370_pcie_wreg: 113 bytes, 24 callsites
r600_rcu_rreg: 111 bytes, 16 callsites
r600_rcu_wreg: 113 bytes, 25 callsites
cik_didt_rreg: 106 bytes, 10 callsites
cik_didt_wreg: 107 bytes, 10 callsites
tn_smc_rreg: 106 bytes, 126 callsites
tn_smc_wreg: 107 bytes, 116 callsites
eg_cg_rreg: 107 bytes, 20 callsites
eg_cg_wreg: 108 bytes, 52 callsites

Functions r100_mm_rreg() and r100_mm_rreg() have a fast path and
a locked (slow) path. This patch deinlines only slow path.

r100_mm_rreg_slow: 78 bytes, 2083 callsites
r100_mm_wreg_slow: 81 bytes, 3570 callsites

Reduction in code size is more than 65,000 bytes:

    text     data      bss       dec     hex filename
85740176 22294680 20627456 128662312 7ab3b28 vmlinux.before
85674192 22294776 20627456 128598664 7aa4288 vmlinux

Signed-off-by: default avatarDenys Vlasenko <dvlasenk@redhat.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: linux-kernel@vger.kernel.org
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b0b9bb4d

drivers/gpu/drm/radeon/cik.c

+25 −0
Original line number Diff line number Diff line
@@ -174,6 +174,31 @@ int cik_get_allowed_info_register(struct radeon_device *rdev, 
	}

}



/*

 * Indirect registers accessor

 */

u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)

{

	unsigned long flags;

	u32 r;



	spin_lock_irqsave(&rdev->didt_idx_lock, flags);

	WREG32(CIK_DIDT_IND_INDEX, (reg));

	r = RREG32(CIK_DIDT_IND_DATA);

	spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);

	return r;

}



void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)

{

	unsigned long flags;



	spin_lock_irqsave(&rdev->didt_idx_lock, flags);

	WREG32(CIK_DIDT_IND_INDEX, (reg));

	WREG32(CIK_DIDT_IND_DATA, (v));

	spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);

}



/* get temperature in millidegrees */

int ci_get_temp(struct radeon_device *rdev)

{

drivers/gpu/drm/radeon/evergreen.c

+69 −0
Original line number Diff line number Diff line
@@ -35,6 +35,75 @@ 
#include "evergreen_blit_shaders.h"

#include "radeon_ucode.h"



/*

 * Indirect registers accessor

 */

u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)

{

	unsigned long flags;

	u32 r;



	spin_lock_irqsave(&rdev->cg_idx_lock, flags);

	WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));

	r = RREG32(EVERGREEN_CG_IND_DATA);

	spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);

	return r;

}



void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)

{

	unsigned long flags;



	spin_lock_irqsave(&rdev->cg_idx_lock, flags);

	WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));

	WREG32(EVERGREEN_CG_IND_DATA, (v));

	spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);

}



u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)

{

	unsigned long flags;

	u32 r;



	spin_lock_irqsave(&rdev->pif_idx_lock, flags);

	WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));

	r = RREG32(EVERGREEN_PIF_PHY0_DATA);

	spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);

	return r;

}



void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)

{

	unsigned long flags;



	spin_lock_irqsave(&rdev->pif_idx_lock, flags);

	WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));

	WREG32(EVERGREEN_PIF_PHY0_DATA, (v));

	spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);

}



u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)

{

	unsigned long flags;

	u32 r;



	spin_lock_irqsave(&rdev->pif_idx_lock, flags);

	WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));

	r = RREG32(EVERGREEN_PIF_PHY1_DATA);

	spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);

	return r;

}



void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)

{

	unsigned long flags;



	spin_lock_irqsave(&rdev->pif_idx_lock, flags);

	WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));

	WREG32(EVERGREEN_PIF_PHY1_DATA, (v));

	spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);

}



static const u32 crtc_offsets[6] =

{

	EVERGREEN_CRTC0_REGISTER_OFFSET,

drivers/gpu/drm/radeon/ni.c

+25 −0
Original line number Diff line number Diff line
@@ -36,6 +36,31 @@ 
#include "radeon_ucode.h"

#include "clearstate_cayman.h"



/*

 * Indirect registers accessor

 */

u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)

{

	unsigned long flags;

	u32 r;



	spin_lock_irqsave(&rdev->smc_idx_lock, flags);

	WREG32(TN_SMC_IND_INDEX_0, (reg));

	r = RREG32(TN_SMC_IND_DATA_0);

	spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);

	return r;

}



void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)

{

	unsigned long flags;



	spin_lock_irqsave(&rdev->smc_idx_lock, flags);

	WREG32(TN_SMC_IND_INDEX_0, (reg));

	WREG32(TN_SMC_IND_DATA_0, (v));

	spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);

}



static const u32 tn_rlc_save_restore_register_list[] =

{

	0x98fc,

drivers/gpu/drm/radeon/r100.c

+22 −0
Original line number Diff line number Diff line
@@ -4090,6 +4090,28 @@ int r100_init(struct radeon_device *rdev) 
	return 0;

}



uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg)

{

	unsigned long flags;

	uint32_t ret;



	spin_lock_irqsave(&rdev->mmio_idx_lock, flags);

	writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);

	ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);

	spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);

	return ret;

}



void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v)

{

	unsigned long flags;



	spin_lock_irqsave(&rdev->mmio_idx_lock, flags);

	writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);

	writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);

	spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);

}



u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)

{

	if (reg < rdev->rio_mem_size)

drivers/gpu/drm/radeon/r300.c

+25 −0
Original line number Diff line number Diff line
@@ -49,6 +49,31 @@ 
 *   tell. (Jerome Glisse)

 */



/*

 * Indirect registers accessor

 */

uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)

{

	unsigned long flags;

	uint32_t r;



	spin_lock_irqsave(&rdev->pcie_idx_lock, flags);

	WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));

	r = RREG32(RADEON_PCIE_DATA);

	spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);

	return r;

}



void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)

{

	unsigned long flags;



	spin_lock_irqsave(&rdev->pcie_idx_lock, flags);

	WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));

	WREG32(RADEON_PCIE_DATA, (v));

	spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);

}



/*

 * rv370,rv380 PCIE GART

 */