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Commit 9e135a2e authored by Bruce Allan's avatar Bruce Allan Committed by David S. Miller
Browse files

e1000e: enable new 82567V-3 device 



This new PCI device ID is for a new combination of MAC and PHY both of
which already have supporting code in the driver, just not yet in this
combination.  During validation of the device, an intermittent issue was
discovered with waking it from a suspended state which can be resolved with
the pre-existing workaround to disable gigabit speed prior to suspending.

Signed-off-by: default avatarBruce Allan <bruce.w.allan@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 1a40d5c1

drivers/net/e1000e/hw.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -356,6 +356,7 @@ enum e1e_registers { 
#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT	0x10BA

#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT	0x10BA

#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT	0x10BB

#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT	0x10BB





#define E1000_DEV_ID_ICH8_82567V_3		0x1501

#define E1000_DEV_ID_ICH8_IGP_M_AMT		0x1049

#define E1000_DEV_ID_ICH8_IGP_M_AMT		0x1049

#define E1000_DEV_ID_ICH8_IGP_AMT		0x104A

#define E1000_DEV_ID_ICH8_IGP_AMT		0x104A

#define E1000_DEV_ID_ICH8_IGP_C			0x104B

#define E1000_DEV_ID_ICH8_IGP_C			0x104B

drivers/net/e1000e/ich8lan.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -3204,6 +3204,7 @@ void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw) 
	u32 phy_ctrl;

	u32 phy_ctrl;





	switch (hw->mac.type) {

	switch (hw->mac.type) {

	case e1000_ich8lan:

	case e1000_ich9lan:

	case e1000_ich9lan:

	case e1000_ich10lan:

	case e1000_ich10lan:

	case e1000_pchlan:

	case e1000_pchlan:

drivers/net/e1000e/netdev.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -5342,6 +5342,7 @@ static struct pci_device_id e1000_pci_tbl[] = { 
	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan },





	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan },