Merge "ARM: dts: msm: add TSPP node for sdm845" (9de60029) · Commits · e / devices / android_kernel_fairphone_FP3

arch/arm64/boot/dts/qcom/sdm845-pinctrl.dtsi

+60 −0

Original line number	Original line	Diff line number	Diff line
	@@ -2796,6 +2796,66 @@
	bias-disable;		bias-disable;
	};		};
	};		};

			tsif0_signals_active: tsif0_signals_active {
			tsif1_clk {
			pins = "gpio89"; /* TSIF0 CLK */
			function = "tsif1_clk";
			};
			tsif1_en {
			pins = "gpio90"; /* TSIF0 Enable */
			function = "tsif1_en";
			};
			tsif1_data {
			pins = "gpio91"; /* TSIF0 DATA */
			function = "tsif1_data";
			};
			signals_cfg {
			pins = "gpio89", "gpio90", "gpio91";
			drive_strength = <2>; /* 2 mA */
			bias-pull-down; /* pull down */
			};
			};

			/* sync signal is only used if configured to mode-2 */
			tsif0_sync_active: tsif0_sync_active {
			tsif1_sync {
			pins = "gpio12"; /* TSIF0 SYNC */
			function = "tsif1_sync";
			drive_strength = <2>; /* 2 mA */
			bias-pull-down; /* pull down */
			};
			};

			tsif1_signals_active: tsif1_signals_active {
			tsif2_clk {
			pins = "gpio93"; /* TSIF1 CLK */
			function = "tsif2_clk";
			};
			tsif2_en {
			pins = "gpio94"; /* TSIF1 Enable */
			function = "tsif2_en";
			};
			tsif2_data {
			pins = "gpio95"; /* TSIF1 DATA */
			function = "tsif2_data";
			};
			signals_cfg {
			pins = "gpio93", "gpio94", "gpio95";
			drive_strength = <2>; /* 2 mA */
			bias-pull-down; /* pull down */
			};
			};

			/* sync signal is only used if configured to mode-2 */
			tsif1_sync_active: tsif1_sync_active {
			tsif2_sync {
			pins = "gpio96"; /* TSIF1 SYNC */
			function = "tsif2_sync";
			drive_strength = <2>; /* 2 mA */
			bias-pull-down; /* pull down */
			};
			};
	};		};
	};		};

arch/arm64/boot/dts/qcom/sdm845.dtsi

+51 −0

Original line number	Original line	Diff line number	Diff line
	@@ -4090,6 +4090,57 @@
	iommus = <&apps_smmu 0x06d6 0x0>;		iommus = <&apps_smmu 0x06d6 0x0>;
	status = "ok";		status = "ok";
	};		};

			tspp: msm_tspp@0x8880000 {
			compatible = "qcom,msm_tspp";
			reg = <0x088a7000 0x200>, /* MSM_TSIF0_PHYS */
			<0x088a8000 0x200>, /* MSM_TSIF1_PHYS */
			<0x088a9000 0x1000>, /* MSM_TSPP_PHYS */
			<0x08884000 0x23000>; /* MSM_TSPP_BAM_PHYS */
			reg-names = "MSM_TSIF0_PHYS",
			"MSM_TSIF1_PHYS",
			"MSM_TSPP_PHYS",
			"MSM_TSPP_BAM_PHYS";
			interrupts = <0 121 0>, /* TSIF_TSPP_IRQ */
			<0 119 0>, /* TSIF0_IRQ */
			<0 120 0>, /* TSIF1_IRQ */
			<0 122 0>; /* TSIF_BAM_IRQ */
			interrupt-names = "TSIF_TSPP_IRQ",
			"TSIF0_IRQ",
			"TSIF1_IRQ",
			"TSIF_BAM_IRQ";

			clock-names = "iface_clk", "ref_clk";
			clocks = <&clock_gcc GCC_TSIF_AHB_CLK>,
			<&clock_gcc GCC_TSIF_REF_CLK>;

			qcom,msm-bus,name = "tsif";
			qcom,msm-bus,num-cases = <2>;
			qcom,msm-bus,num-paths = <1>;
			qcom,msm-bus,vectors-KBps =
			<82 512 0 0>, /* No vote */
			<82 512 12288 24576>;
			/* Max. bandwidth, 2xTSIF, each max of 96Mbps */

			pinctrl-names = "disabled",
			"tsif0-mode1", "tsif0-mode2",
			"tsif1-mode1", "tsif1-mode2",
			"dual-tsif-mode1", "dual-tsif-mode2";

			pinctrl-0 = <>; /* disabled */
			pinctrl-1 = <&tsif0_signals_active>; /* tsif0-mode1 */
			pinctrl-2 = <&tsif0_signals_active
			&tsif0_sync_active>; /* tsif0-mode2 */
			pinctrl-3 = <&tsif1_signals_active>; /* tsif1-mode1 */
			pinctrl-4 = <&tsif1_signals_active
			&tsif1_sync_active>; /* tsif1-mode2 */
			pinctrl-5 = <&tsif0_signals_active
			&tsif1_signals_active>; /* dual-tsif-mode1 */
			pinctrl-6 = <&tsif0_signals_active
			&tsif0_sync_active
			&tsif1_signals_active
			&tsif1_sync_active>; /* dual-tsif-mode2 */
			};
	};		};

	&clock_cpucc {		&clock_cpucc {