Loading arch/arm/kernel/sys_arm.c +1 −1 Original line number Diff line number Diff line Loading @@ -305,7 +305,7 @@ long execve(const char *filename, char **argv, char **envp) "Ir" (THREAD_START_SP - sizeof(regs)), "r" (®s), "Ir" (sizeof(regs)) : "r0", "r1", "r2", "r3", "ip", "memory"); : "r0", "r1", "r2", "r3", "ip", "lr", "memory"); out: return ret; Loading arch/arm/kernel/traps.c +1 −1 Original line number Diff line number Diff line Loading @@ -504,7 +504,7 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs) bad_access: spin_unlock(&mm->page_table_lock); /* simulate a read access fault */ /* simulate a write access fault */ do_DataAbort(addr, 15 + (1 << 11), regs); return -1; } Loading arch/arm/mach-imx/generic.c +12 −11 Original line number Diff line number Diff line Loading @@ -28,14 +28,15 @@ #include <linux/module.h> #include <asm/arch/imxfb.h> #include <asm/hardware.h> #include <asm/arch/imx-regs.h> #include <asm/mach/map.h> void imx_gpio_mode(int gpio_mode) { unsigned int pin = gpio_mode & GPIO_PIN_MASK; unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> 5; unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> 10; unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT; unsigned int tmp; /* Pullup enable */ Loading @@ -57,7 +58,7 @@ void imx_gpio_mode(int gpio_mode) GPR(port) &= ~(1<<pin); /* use as gpio? */ if( ocr == 3 ) if(gpio_mode & GPIO_GIUS) GIUS(port) |= (1<<pin); else GIUS(port) &= ~(1<<pin); Loading @@ -72,20 +73,20 @@ void imx_gpio_mode(int gpio_mode) tmp |= (ocr << (pin*2)); OCR1(port) = tmp; if( gpio_mode & GPIO_AOUT ) ICONFA1(port) &= ~( 3<<(pin*2)); if( gpio_mode & GPIO_BOUT ) ICONFA1(port) |= ((gpio_mode >> GPIO_AOUT_SHIFT) & 3) << (pin * 2); ICONFB1(port) &= ~( 3<<(pin*2)); ICONFB1(port) |= ((gpio_mode >> GPIO_BOUT_SHIFT) & 3) << (pin * 2); } else { tmp = OCR2(port); tmp &= ~( 3<<((pin-16)*2)); tmp |= (ocr << ((pin-16)*2)); OCR2(port) = tmp; if( gpio_mode & GPIO_AOUT ) ICONFA2(port) &= ~( 3<<((pin-16)*2)); if( gpio_mode & GPIO_BOUT ) ICONFA2(port) |= ((gpio_mode >> GPIO_AOUT_SHIFT) & 3) << ((pin-16) * 2); ICONFB2(port) &= ~( 3<<((pin-16)*2)); ICONFB2(port) |= ((gpio_mode >> GPIO_BOUT_SHIFT) & 3) << ((pin-16) * 2); } } Loading arch/arm/mach-imx/mx1ads.c +1 −1 Original line number Diff line number Diff line Loading @@ -55,7 +55,7 @@ static void __init mx1ads_init(void) { #ifdef CONFIG_LEDS imx_gpio_mode(GPIO_PORTA | GPIO_OUT | GPIO_GPIO | 2); imx_gpio_mode(GPIO_PORTA | GPIO_OUT | 2); #endif platform_add_devices(devices, ARRAY_SIZE(devices)); } Loading arch/arm/mm/Kconfig +4 −4 Original line number Diff line number Diff line Loading @@ -370,21 +370,21 @@ config CPU_BIG_ENDIAN config CPU_ICACHE_DISABLE bool "Disable I-Cache" depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6 help Say Y here to disable the processor instruction cache. Unless you have a reason not to or are unsure, say N. config CPU_DCACHE_DISABLE bool "Disable D-Cache" depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6 help Say Y here to disable the processor data cache. Unless you have a reason not to or are unsure, say N. config CPU_DCACHE_WRITETHROUGH bool "Force write through D-cache" depends on (CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020) && !CPU_DCACHE_DISABLE depends on (CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6) && !CPU_DCACHE_DISABLE default y if CPU_ARM925T help Say Y here to use the data cache in writethrough mode. Unless you Loading @@ -399,7 +399,7 @@ config CPU_CACHE_ROUND_ROBIN config CPU_BPREDICT_DISABLE bool "Disable branch prediction" depends on CPU_ARM1020 depends on CPU_ARM1020 || CPU_V6 help Say Y here to disable branch prediction. If unsure, say N. Loading Loading
arch/arm/kernel/sys_arm.c +1 −1 Original line number Diff line number Diff line Loading @@ -305,7 +305,7 @@ long execve(const char *filename, char **argv, char **envp) "Ir" (THREAD_START_SP - sizeof(regs)), "r" (®s), "Ir" (sizeof(regs)) : "r0", "r1", "r2", "r3", "ip", "memory"); : "r0", "r1", "r2", "r3", "ip", "lr", "memory"); out: return ret; Loading
arch/arm/kernel/traps.c +1 −1 Original line number Diff line number Diff line Loading @@ -504,7 +504,7 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs) bad_access: spin_unlock(&mm->page_table_lock); /* simulate a read access fault */ /* simulate a write access fault */ do_DataAbort(addr, 15 + (1 << 11), regs); return -1; } Loading
arch/arm/mach-imx/generic.c +12 −11 Original line number Diff line number Diff line Loading @@ -28,14 +28,15 @@ #include <linux/module.h> #include <asm/arch/imxfb.h> #include <asm/hardware.h> #include <asm/arch/imx-regs.h> #include <asm/mach/map.h> void imx_gpio_mode(int gpio_mode) { unsigned int pin = gpio_mode & GPIO_PIN_MASK; unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> 5; unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> 10; unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT; unsigned int tmp; /* Pullup enable */ Loading @@ -57,7 +58,7 @@ void imx_gpio_mode(int gpio_mode) GPR(port) &= ~(1<<pin); /* use as gpio? */ if( ocr == 3 ) if(gpio_mode & GPIO_GIUS) GIUS(port) |= (1<<pin); else GIUS(port) &= ~(1<<pin); Loading @@ -72,20 +73,20 @@ void imx_gpio_mode(int gpio_mode) tmp |= (ocr << (pin*2)); OCR1(port) = tmp; if( gpio_mode & GPIO_AOUT ) ICONFA1(port) &= ~( 3<<(pin*2)); if( gpio_mode & GPIO_BOUT ) ICONFA1(port) |= ((gpio_mode >> GPIO_AOUT_SHIFT) & 3) << (pin * 2); ICONFB1(port) &= ~( 3<<(pin*2)); ICONFB1(port) |= ((gpio_mode >> GPIO_BOUT_SHIFT) & 3) << (pin * 2); } else { tmp = OCR2(port); tmp &= ~( 3<<((pin-16)*2)); tmp |= (ocr << ((pin-16)*2)); OCR2(port) = tmp; if( gpio_mode & GPIO_AOUT ) ICONFA2(port) &= ~( 3<<((pin-16)*2)); if( gpio_mode & GPIO_BOUT ) ICONFA2(port) |= ((gpio_mode >> GPIO_AOUT_SHIFT) & 3) << ((pin-16) * 2); ICONFB2(port) &= ~( 3<<((pin-16)*2)); ICONFB2(port) |= ((gpio_mode >> GPIO_BOUT_SHIFT) & 3) << ((pin-16) * 2); } } Loading
arch/arm/mach-imx/mx1ads.c +1 −1 Original line number Diff line number Diff line Loading @@ -55,7 +55,7 @@ static void __init mx1ads_init(void) { #ifdef CONFIG_LEDS imx_gpio_mode(GPIO_PORTA | GPIO_OUT | GPIO_GPIO | 2); imx_gpio_mode(GPIO_PORTA | GPIO_OUT | 2); #endif platform_add_devices(devices, ARRAY_SIZE(devices)); } Loading
arch/arm/mm/Kconfig +4 −4 Original line number Diff line number Diff line Loading @@ -370,21 +370,21 @@ config CPU_BIG_ENDIAN config CPU_ICACHE_DISABLE bool "Disable I-Cache" depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6 help Say Y here to disable the processor instruction cache. Unless you have a reason not to or are unsure, say N. config CPU_DCACHE_DISABLE bool "Disable D-Cache" depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6 help Say Y here to disable the processor data cache. Unless you have a reason not to or are unsure, say N. config CPU_DCACHE_WRITETHROUGH bool "Force write through D-cache" depends on (CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020) && !CPU_DCACHE_DISABLE depends on (CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6) && !CPU_DCACHE_DISABLE default y if CPU_ARM925T help Say Y here to use the data cache in writethrough mode. Unless you Loading @@ -399,7 +399,7 @@ config CPU_CACHE_ROUND_ROBIN config CPU_BPREDICT_DISABLE bool "Disable branch prediction" depends on CPU_ARM1020 depends on CPU_ARM1020 || CPU_V6 help Say Y here to disable branch prediction. If unsure, say N. Loading