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Commit 9d5715f9 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-fixes-4.2' of git://people.freedesktop.org/~agd5f/linux into drm-fixes 

radeon and amdgpu fixes for 4.2.  All over the place:
- fix cursor corruption on resume and re-enable no VT switch on suspend
- vblank fixes
- fix gpuvm error messages
- misc other fixes

* 'drm-fixes-4.2' of git://people.freedesktop.org/~agd5f/linux:
  drm/radeon: disable vce init on cayman (v2)
  drm/amdgpu: fix timeout calculation
  drm/radeon: check if BO_VA is set before adding it to the invalidation list
  drm/radeon: allways add the VM clear duplicate
  Revert "Revert "drm/radeon: dont switch vt on suspend""
  drm/radeon: Fold radeon_set_cursor() into radeon_show_cursor()
  drm/radeon: unpin cursor BOs on suspend and pin them again on resume (v2)
  drm/radeon: Clean up reference counting and pinning of the cursor BOs
  drm/radeon: fix underflow in r600_cp_dispatch_texture()
  drm/radeon: default to 2048 MB GART size on SI+
  drm/radeon: fix HDP flushing
  drm/radeon: use RCU query for GEM_BUSY syscall
  drm/amdgpu: Handle irqs only based on irq ring, not irq status regs.
  drm/radeon: Handle irqs only based on irq ring, not irq status regs.
parents c4b5fd3f 355c8228

drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -352,7 +352,7 @@ unsigned long amdgpu_gem_timeout(uint64_t timeout_ns) 
	if (((int64_t)timeout_ns) < 0)

	if (((int64_t)timeout_ns) < 0)

		return MAX_SCHEDULE_TIMEOUT;

		return MAX_SCHEDULE_TIMEOUT;





	timeout = ktime_sub_ns(ktime_get(), timeout_ns);

	timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get());

	if (ktime_to_ns(timeout) < 0)

	if (ktime_to_ns(timeout) < 0)

		return 0;

		return 0;

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

+14 −8
Original line number Original line Diff line number Diff line
@@ -3403,19 +3403,25 @@ static int dce_v10_0_crtc_irq(struct amdgpu_device *adev, 




	switch (entry->src_data) {

	switch (entry->src_data) {

	case 0: /* vblank */

	case 0: /* vblank */

		if (disp_int & interrupt_status_offsets[crtc].vblank) {

		if (disp_int & interrupt_status_offsets[crtc].vblank)

			dce_v10_0_crtc_vblank_int_ack(adev, crtc);

			dce_v10_0_crtc_vblank_int_ack(adev, crtc);

		else

			DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");



		if (amdgpu_irq_enabled(adev, source, irq_type)) {

		if (amdgpu_irq_enabled(adev, source, irq_type)) {

			drm_handle_vblank(adev->ddev, crtc);

			drm_handle_vblank(adev->ddev, crtc);

		}

		}

		DRM_DEBUG("IH: D%d vblank\n", crtc + 1);

		DRM_DEBUG("IH: D%d vblank\n", crtc + 1);

		}



		break;

		break;

	case 1: /* vline */

	case 1: /* vline */

		if (disp_int & interrupt_status_offsets[crtc].vline) {

		if (disp_int & interrupt_status_offsets[crtc].vline)

			dce_v10_0_crtc_vline_int_ack(adev, crtc);

			dce_v10_0_crtc_vline_int_ack(adev, crtc);

		else

			DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");



		DRM_DEBUG("IH: D%d vline\n", crtc + 1);

		DRM_DEBUG("IH: D%d vline\n", crtc + 1);

		}



		break;

		break;

	default:

	default:

		DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);

		DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);

drivers/gpu/drm/amd/amdgpu/dce_v11_0.c

+14 −8
Original line number Original line Diff line number Diff line
@@ -3402,19 +3402,25 @@ static int dce_v11_0_crtc_irq(struct amdgpu_device *adev, 




	switch (entry->src_data) {

	switch (entry->src_data) {

	case 0: /* vblank */

	case 0: /* vblank */

		if (disp_int & interrupt_status_offsets[crtc].vblank) {

		if (disp_int & interrupt_status_offsets[crtc].vblank)

			dce_v11_0_crtc_vblank_int_ack(adev, crtc);

			dce_v11_0_crtc_vblank_int_ack(adev, crtc);

		else

			DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");



		if (amdgpu_irq_enabled(adev, source, irq_type)) {

		if (amdgpu_irq_enabled(adev, source, irq_type)) {

			drm_handle_vblank(adev->ddev, crtc);

			drm_handle_vblank(adev->ddev, crtc);

		}

		}

		DRM_DEBUG("IH: D%d vblank\n", crtc + 1);

		DRM_DEBUG("IH: D%d vblank\n", crtc + 1);

		}



		break;

		break;

	case 1: /* vline */

	case 1: /* vline */

		if (disp_int & interrupt_status_offsets[crtc].vline) {

		if (disp_int & interrupt_status_offsets[crtc].vline)

			dce_v11_0_crtc_vline_int_ack(adev, crtc);

			dce_v11_0_crtc_vline_int_ack(adev, crtc);

		else

			DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");



		DRM_DEBUG("IH: D%d vline\n", crtc + 1);

		DRM_DEBUG("IH: D%d vline\n", crtc + 1);

		}



		break;

		break;

	default:

	default:

		DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);

		DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

+14 −8
Original line number Original line Diff line number Diff line
@@ -3237,19 +3237,25 @@ static int dce_v8_0_crtc_irq(struct amdgpu_device *adev, 




	switch (entry->src_data) {

	switch (entry->src_data) {

	case 0: /* vblank */

	case 0: /* vblank */

		if (disp_int & interrupt_status_offsets[crtc].vblank) {

		if (disp_int & interrupt_status_offsets[crtc].vblank)

			WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], LB_VBLANK_STATUS__VBLANK_ACK_MASK);

			WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], LB_VBLANK_STATUS__VBLANK_ACK_MASK);

		else

			DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");



		if (amdgpu_irq_enabled(adev, source, irq_type)) {

		if (amdgpu_irq_enabled(adev, source, irq_type)) {

			drm_handle_vblank(adev->ddev, crtc);

			drm_handle_vblank(adev->ddev, crtc);

		}

		}

		DRM_DEBUG("IH: D%d vblank\n", crtc + 1);

		DRM_DEBUG("IH: D%d vblank\n", crtc + 1);

		}



		break;

		break;

	case 1: /* vline */

	case 1: /* vline */

		if (disp_int & interrupt_status_offsets[crtc].vline) {

		if (disp_int & interrupt_status_offsets[crtc].vline)

			WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], LB_VLINE_STATUS__VLINE_ACK_MASK);

			WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], LB_VLINE_STATUS__VLINE_ACK_MASK);

		else

			DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");



		DRM_DEBUG("IH: D%d vline\n", crtc + 1);

		DRM_DEBUG("IH: D%d vline\n", crtc + 1);

		}



		break;

		break;

	default:

	default:

		DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);

		DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);

drivers/gpu/drm/radeon/cik.c

+192 −144
Original line number Original line Diff line number Diff line
@@ -7964,7 +7964,9 @@ int cik_irq_process(struct radeon_device *rdev) 
		case 1: /* D1 vblank/vline */

		case 1: /* D1 vblank/vline */

			switch (src_data) {

			switch (src_data) {

			case 0: /* D1 vblank */

			case 0: /* D1 vblank */

				if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VBLANK_INTERRUPT) {

				if (!(rdev->irq.stat_regs.cik.disp_int & LB_D1_VBLANK_INTERRUPT))

					DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");



				if (rdev->irq.crtc_vblank_int[0]) {

				if (rdev->irq.crtc_vblank_int[0]) {

					drm_handle_vblank(rdev->ddev, 0);

					drm_handle_vblank(rdev->ddev, 0);

					rdev->pm.vblank_sync = true;

					rdev->pm.vblank_sync = true;
@@ -7974,13 +7976,15 @@ int cik_irq_process(struct radeon_device *rdev) 
					radeon_crtc_handle_vblank(rdev, 0);

					radeon_crtc_handle_vblank(rdev, 0);

				rdev->irq.stat_regs.cik.disp_int &= ~LB_D1_VBLANK_INTERRUPT;

				rdev->irq.stat_regs.cik.disp_int &= ~LB_D1_VBLANK_INTERRUPT;

				DRM_DEBUG("IH: D1 vblank\n");

				DRM_DEBUG("IH: D1 vblank\n");

				}



				break;

				break;

			case 1: /* D1 vline */

			case 1: /* D1 vline */

				if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VLINE_INTERRUPT) {

				if (!(rdev->irq.stat_regs.cik.disp_int & LB_D1_VLINE_INTERRUPT))

					DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");



				rdev->irq.stat_regs.cik.disp_int &= ~LB_D1_VLINE_INTERRUPT;

				rdev->irq.stat_regs.cik.disp_int &= ~LB_D1_VLINE_INTERRUPT;

				DRM_DEBUG("IH: D1 vline\n");

				DRM_DEBUG("IH: D1 vline\n");

				}



				break;

				break;

			default:

			default:

				DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);

				DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
@@ -7990,7 +7994,9 @@ int cik_irq_process(struct radeon_device *rdev) 
		case 2: /* D2 vblank/vline */

		case 2: /* D2 vblank/vline */

			switch (src_data) {

			switch (src_data) {

			case 0: /* D2 vblank */

			case 0: /* D2 vblank */

				if (rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {

				if (!(rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VBLANK_INTERRUPT))

					DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");



				if (rdev->irq.crtc_vblank_int[1]) {

				if (rdev->irq.crtc_vblank_int[1]) {

					drm_handle_vblank(rdev->ddev, 1);

					drm_handle_vblank(rdev->ddev, 1);

					rdev->pm.vblank_sync = true;

					rdev->pm.vblank_sync = true;
@@ -8000,13 +8006,15 @@ int cik_irq_process(struct radeon_device *rdev) 
					radeon_crtc_handle_vblank(rdev, 1);

					radeon_crtc_handle_vblank(rdev, 1);

				rdev->irq.stat_regs.cik.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;

				rdev->irq.stat_regs.cik.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;

				DRM_DEBUG("IH: D2 vblank\n");

				DRM_DEBUG("IH: D2 vblank\n");

				}



				break;

				break;

			case 1: /* D2 vline */

			case 1: /* D2 vline */

				if (rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VLINE_INTERRUPT) {

				if (!(rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VLINE_INTERRUPT))

					DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");



				rdev->irq.stat_regs.cik.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;

				rdev->irq.stat_regs.cik.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;

				DRM_DEBUG("IH: D2 vline\n");

				DRM_DEBUG("IH: D2 vline\n");

				}



				break;

				break;

			default:

			default:

				DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);

				DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
@@ -8016,7 +8024,9 @@ int cik_irq_process(struct radeon_device *rdev) 
		case 3: /* D3 vblank/vline */

		case 3: /* D3 vblank/vline */

			switch (src_data) {

			switch (src_data) {

			case 0: /* D3 vblank */

			case 0: /* D3 vblank */

				if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {

				if (!(rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT))

					DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");



				if (rdev->irq.crtc_vblank_int[2]) {

				if (rdev->irq.crtc_vblank_int[2]) {

					drm_handle_vblank(rdev->ddev, 2);

					drm_handle_vblank(rdev->ddev, 2);

					rdev->pm.vblank_sync = true;

					rdev->pm.vblank_sync = true;
@@ -8026,13 +8036,15 @@ int cik_irq_process(struct radeon_device *rdev) 
					radeon_crtc_handle_vblank(rdev, 2);

					radeon_crtc_handle_vblank(rdev, 2);

				rdev->irq.stat_regs.cik.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;

				rdev->irq.stat_regs.cik.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;

				DRM_DEBUG("IH: D3 vblank\n");

				DRM_DEBUG("IH: D3 vblank\n");

				}



				break;

				break;

			case 1: /* D3 vline */

			case 1: /* D3 vline */

				if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {

				if (!(rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VLINE_INTERRUPT))

					DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");



				rdev->irq.stat_regs.cik.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;

				rdev->irq.stat_regs.cik.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;

				DRM_DEBUG("IH: D3 vline\n");

				DRM_DEBUG("IH: D3 vline\n");

				}



				break;

				break;

			default:

			default:

				DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);

				DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
@@ -8042,7 +8054,9 @@ int cik_irq_process(struct radeon_device *rdev) 
		case 4: /* D4 vblank/vline */

		case 4: /* D4 vblank/vline */

			switch (src_data) {

			switch (src_data) {

			case 0: /* D4 vblank */

			case 0: /* D4 vblank */

				if (rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {

				if (!(rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT))

					DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");



				if (rdev->irq.crtc_vblank_int[3]) {

				if (rdev->irq.crtc_vblank_int[3]) {

					drm_handle_vblank(rdev->ddev, 3);

					drm_handle_vblank(rdev->ddev, 3);

					rdev->pm.vblank_sync = true;

					rdev->pm.vblank_sync = true;
@@ -8052,13 +8066,15 @@ int cik_irq_process(struct radeon_device *rdev) 
					radeon_crtc_handle_vblank(rdev, 3);

					radeon_crtc_handle_vblank(rdev, 3);

				rdev->irq.stat_regs.cik.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;

				rdev->irq.stat_regs.cik.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;

				DRM_DEBUG("IH: D4 vblank\n");

				DRM_DEBUG("IH: D4 vblank\n");

				}



				break;

				break;

			case 1: /* D4 vline */

			case 1: /* D4 vline */

				if (rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {

				if (!(rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VLINE_INTERRUPT))

					DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");



				rdev->irq.stat_regs.cik.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;

				rdev->irq.stat_regs.cik.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;

				DRM_DEBUG("IH: D4 vline\n");

				DRM_DEBUG("IH: D4 vline\n");

				}



				break;

				break;

			default:

			default:

				DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);

				DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
@@ -8068,7 +8084,9 @@ int cik_irq_process(struct radeon_device *rdev) 
		case 5: /* D5 vblank/vline */

		case 5: /* D5 vblank/vline */

			switch (src_data) {

			switch (src_data) {

			case 0: /* D5 vblank */

			case 0: /* D5 vblank */

				if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {

				if (!(rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT))

					DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");



				if (rdev->irq.crtc_vblank_int[4]) {

				if (rdev->irq.crtc_vblank_int[4]) {

					drm_handle_vblank(rdev->ddev, 4);

					drm_handle_vblank(rdev->ddev, 4);

					rdev->pm.vblank_sync = true;

					rdev->pm.vblank_sync = true;
@@ -8078,13 +8096,15 @@ int cik_irq_process(struct radeon_device *rdev) 
					radeon_crtc_handle_vblank(rdev, 4);

					radeon_crtc_handle_vblank(rdev, 4);

				rdev->irq.stat_regs.cik.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;

				rdev->irq.stat_regs.cik.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;

				DRM_DEBUG("IH: D5 vblank\n");

				DRM_DEBUG("IH: D5 vblank\n");

				}



				break;

				break;

			case 1: /* D5 vline */

			case 1: /* D5 vline */

				if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {

				if (!(rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VLINE_INTERRUPT))

					DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");



				rdev->irq.stat_regs.cik.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;

				rdev->irq.stat_regs.cik.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;

				DRM_DEBUG("IH: D5 vline\n");

				DRM_DEBUG("IH: D5 vline\n");

				}



				break;

				break;

			default:

			default:

				DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);

				DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
@@ -8094,7 +8114,9 @@ int cik_irq_process(struct radeon_device *rdev) 
		case 6: /* D6 vblank/vline */

		case 6: /* D6 vblank/vline */

			switch (src_data) {

			switch (src_data) {

			case 0: /* D6 vblank */

			case 0: /* D6 vblank */

				if (rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {

				if (!(rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT))

					DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");



				if (rdev->irq.crtc_vblank_int[5]) {

				if (rdev->irq.crtc_vblank_int[5]) {

					drm_handle_vblank(rdev->ddev, 5);

					drm_handle_vblank(rdev->ddev, 5);

					rdev->pm.vblank_sync = true;

					rdev->pm.vblank_sync = true;
@@ -8104,13 +8126,15 @@ int cik_irq_process(struct radeon_device *rdev) 
					radeon_crtc_handle_vblank(rdev, 5);

					radeon_crtc_handle_vblank(rdev, 5);

				rdev->irq.stat_regs.cik.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;

				rdev->irq.stat_regs.cik.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;

				DRM_DEBUG("IH: D6 vblank\n");

				DRM_DEBUG("IH: D6 vblank\n");

				}



				break;

				break;

			case 1: /* D6 vline */

			case 1: /* D6 vline */

				if (rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {

				if (!(rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VLINE_INTERRUPT))

					DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");



				rdev->irq.stat_regs.cik.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;

				rdev->irq.stat_regs.cik.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;

				DRM_DEBUG("IH: D6 vline\n");

				DRM_DEBUG("IH: D6 vline\n");

				}



				break;

				break;

			default:

			default:

				DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);

				DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
@@ -8130,88 +8154,112 @@ int cik_irq_process(struct radeon_device *rdev) 
		case 42: /* HPD hotplug */

		case 42: /* HPD hotplug */

			switch (src_data) {

			switch (src_data) {

			case 0:

			case 0:

				if (rdev->irq.stat_regs.cik.disp_int & DC_HPD1_INTERRUPT) {

				if (!(rdev->irq.stat_regs.cik.disp_int & DC_HPD1_INTERRUPT))

					DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");



				rdev->irq.stat_regs.cik.disp_int &= ~DC_HPD1_INTERRUPT;

				rdev->irq.stat_regs.cik.disp_int &= ~DC_HPD1_INTERRUPT;

				queue_hotplug = true;

				queue_hotplug = true;

				DRM_DEBUG("IH: HPD1\n");

				DRM_DEBUG("IH: HPD1\n");

				}



				break;

				break;

			case 1:

			case 1:

				if (rdev->irq.stat_regs.cik.disp_int_cont & DC_HPD2_INTERRUPT) {

				if (!(rdev->irq.stat_regs.cik.disp_int_cont & DC_HPD2_INTERRUPT))

					DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");



				rdev->irq.stat_regs.cik.disp_int_cont &= ~DC_HPD2_INTERRUPT;

				rdev->irq.stat_regs.cik.disp_int_cont &= ~DC_HPD2_INTERRUPT;

				queue_hotplug = true;

				queue_hotplug = true;

				DRM_DEBUG("IH: HPD2\n");

				DRM_DEBUG("IH: HPD2\n");

				}



				break;

				break;

			case 2:

			case 2:

				if (rdev->irq.stat_regs.cik.disp_int_cont2 & DC_HPD3_INTERRUPT) {

				if (!(rdev->irq.stat_regs.cik.disp_int_cont2 & DC_HPD3_INTERRUPT))

					DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");



				rdev->irq.stat_regs.cik.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;

				rdev->irq.stat_regs.cik.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;

				queue_hotplug = true;

				queue_hotplug = true;

				DRM_DEBUG("IH: HPD3\n");

				DRM_DEBUG("IH: HPD3\n");

				}



				break;

				break;

			case 3:

			case 3:

				if (rdev->irq.stat_regs.cik.disp_int_cont3 & DC_HPD4_INTERRUPT) {

				if (!(rdev->irq.stat_regs.cik.disp_int_cont3 & DC_HPD4_INTERRUPT))

					DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");



				rdev->irq.stat_regs.cik.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;

				rdev->irq.stat_regs.cik.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;

				queue_hotplug = true;

				queue_hotplug = true;

				DRM_DEBUG("IH: HPD4\n");

				DRM_DEBUG("IH: HPD4\n");

				}



				break;

				break;

			case 4:

			case 4:

				if (rdev->irq.stat_regs.cik.disp_int_cont4 & DC_HPD5_INTERRUPT) {

				if (!(rdev->irq.stat_regs.cik.disp_int_cont4 & DC_HPD5_INTERRUPT))

					DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");



				rdev->irq.stat_regs.cik.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;

				rdev->irq.stat_regs.cik.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;

				queue_hotplug = true;

				queue_hotplug = true;

				DRM_DEBUG("IH: HPD5\n");

				DRM_DEBUG("IH: HPD5\n");

				}



				break;

				break;

			case 5:

			case 5:

				if (rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_INTERRUPT) {

				if (!(rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_INTERRUPT))

					DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");



				rdev->irq.stat_regs.cik.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;

				rdev->irq.stat_regs.cik.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;

				queue_hotplug = true;

				queue_hotplug = true;

				DRM_DEBUG("IH: HPD6\n");

				DRM_DEBUG("IH: HPD6\n");

				}



				break;

				break;

			case 6:

			case 6:

				if (rdev->irq.stat_regs.cik.disp_int & DC_HPD1_RX_INTERRUPT) {

				if (!(rdev->irq.stat_regs.cik.disp_int & DC_HPD1_RX_INTERRUPT))

					DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");



				rdev->irq.stat_regs.cik.disp_int &= ~DC_HPD1_RX_INTERRUPT;

				rdev->irq.stat_regs.cik.disp_int &= ~DC_HPD1_RX_INTERRUPT;

				queue_dp = true;

				queue_dp = true;

				DRM_DEBUG("IH: HPD_RX 1\n");

				DRM_DEBUG("IH: HPD_RX 1\n");

				}



				break;

				break;

			case 7:

			case 7:

				if (rdev->irq.stat_regs.cik.disp_int_cont & DC_HPD2_RX_INTERRUPT) {

				if (!(rdev->irq.stat_regs.cik.disp_int_cont & DC_HPD2_RX_INTERRUPT))

					DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");



				rdev->irq.stat_regs.cik.disp_int_cont &= ~DC_HPD2_RX_INTERRUPT;

				rdev->irq.stat_regs.cik.disp_int_cont &= ~DC_HPD2_RX_INTERRUPT;

				queue_dp = true;

				queue_dp = true;

				DRM_DEBUG("IH: HPD_RX 2\n");

				DRM_DEBUG("IH: HPD_RX 2\n");

				}



				break;

				break;

			case 8:

			case 8:

				if (rdev->irq.stat_regs.cik.disp_int_cont2 & DC_HPD3_RX_INTERRUPT) {

				if (!(rdev->irq.stat_regs.cik.disp_int_cont2 & DC_HPD3_RX_INTERRUPT))

					DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");



				rdev->irq.stat_regs.cik.disp_int_cont2 &= ~DC_HPD3_RX_INTERRUPT;

				rdev->irq.stat_regs.cik.disp_int_cont2 &= ~DC_HPD3_RX_INTERRUPT;

				queue_dp = true;

				queue_dp = true;

				DRM_DEBUG("IH: HPD_RX 3\n");

				DRM_DEBUG("IH: HPD_RX 3\n");

				}



				break;

				break;

			case 9:

			case 9:

				if (rdev->irq.stat_regs.cik.disp_int_cont3 & DC_HPD4_RX_INTERRUPT) {

				if (!(rdev->irq.stat_regs.cik.disp_int_cont3 & DC_HPD4_RX_INTERRUPT))

					DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");



				rdev->irq.stat_regs.cik.disp_int_cont3 &= ~DC_HPD4_RX_INTERRUPT;

				rdev->irq.stat_regs.cik.disp_int_cont3 &= ~DC_HPD4_RX_INTERRUPT;

				queue_dp = true;

				queue_dp = true;

				DRM_DEBUG("IH: HPD_RX 4\n");

				DRM_DEBUG("IH: HPD_RX 4\n");

				}



				break;

				break;

			case 10:

			case 10:

				if (rdev->irq.stat_regs.cik.disp_int_cont4 & DC_HPD5_RX_INTERRUPT) {

				if (!(rdev->irq.stat_regs.cik.disp_int_cont4 & DC_HPD5_RX_INTERRUPT))

					DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");



				rdev->irq.stat_regs.cik.disp_int_cont4 &= ~DC_HPD5_RX_INTERRUPT;

				rdev->irq.stat_regs.cik.disp_int_cont4 &= ~DC_HPD5_RX_INTERRUPT;

				queue_dp = true;

				queue_dp = true;

				DRM_DEBUG("IH: HPD_RX 5\n");

				DRM_DEBUG("IH: HPD_RX 5\n");

				}



				break;

				break;

			case 11:

			case 11:

				if (rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_RX_INTERRUPT) {

				if (!(rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_RX_INTERRUPT))

					DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");



				rdev->irq.stat_regs.cik.disp_int_cont5 &= ~DC_HPD6_RX_INTERRUPT;

				rdev->irq.stat_regs.cik.disp_int_cont5 &= ~DC_HPD6_RX_INTERRUPT;

				queue_dp = true;

				queue_dp = true;

				DRM_DEBUG("IH: HPD_RX 6\n");

				DRM_DEBUG("IH: HPD_RX 6\n");

				}



				break;

				break;

			default:

			default:

				DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);

				DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);