Loading drivers/gpu/drm/msm/sde/sde_encoder_phys.h +3 −0 Original line number Diff line number Diff line Loading @@ -236,6 +236,8 @@ struct sde_encoder_phys_vid { * For CMD encoders, VBLANK is driven by the PP RD Done IRQ * @pp_tx_done_irq_idx: IRQ signifying frame transmission to panel complete * @irq_cb: interrupt callback * @serialize_wait4pp: serialize wait4pp feature waits for pp_done interrupt * after ctl_start instead of before next frame kickoff */ struct sde_encoder_phys_cmd { struct sde_encoder_phys base; Loading @@ -243,6 +245,7 @@ struct sde_encoder_phys_cmd { int stream_sel; int irq_idx[INTR_IDX_MAX]; struct sde_irq_callback irq_cb[INTR_IDX_MAX]; bool serialize_wait4pp; }; /** Loading drivers/gpu/drm/msm/sde/sde_encoder_phys_cmd.c +20 −12 Original line number Diff line number Diff line Loading @@ -591,18 +591,6 @@ static void sde_encoder_phys_cmd_get_hw_resources( hw_res->intfs[cmd_enc->intf_idx - INTF_0] = INTF_MODE_CMD; } static int sde_encoder_phys_cmd_wait_for_commit_done( struct sde_encoder_phys *phys_enc) { /* * Since ctl_start "commits" the transaction to hardware, and the * tearcheck block takes it from there, there is no need to have a * separate wait for committed, a la wait-for-vsync in video mode */ return 0; } static void sde_encoder_phys_cmd_prepare_for_kickoff( struct sde_encoder_phys *phys_enc) { Loading Loading @@ -631,6 +619,26 @@ static void sde_encoder_phys_cmd_prepare_for_kickoff( } } static int sde_encoder_phys_cmd_wait_for_commit_done( struct sde_encoder_phys *phys_enc) { struct sde_encoder_phys_cmd *cmd_enc = to_sde_encoder_phys_cmd(phys_enc); if (cmd_enc->serialize_wait4pp) sde_encoder_phys_cmd_prepare_for_kickoff(phys_enc); /* * following statement is true serialize_wait4pp is false. * * Since ctl_start "commits" the transaction to hardware, and the * tearcheck block takes it from there, there is no need to have a * separate wait for committed, a la wait-for-vsync in video mode */ return 0; } static void sde_encoder_phys_cmd_init_ops( struct sde_encoder_phys_ops *ops) { Loading Loading
drivers/gpu/drm/msm/sde/sde_encoder_phys.h +3 −0 Original line number Diff line number Diff line Loading @@ -236,6 +236,8 @@ struct sde_encoder_phys_vid { * For CMD encoders, VBLANK is driven by the PP RD Done IRQ * @pp_tx_done_irq_idx: IRQ signifying frame transmission to panel complete * @irq_cb: interrupt callback * @serialize_wait4pp: serialize wait4pp feature waits for pp_done interrupt * after ctl_start instead of before next frame kickoff */ struct sde_encoder_phys_cmd { struct sde_encoder_phys base; Loading @@ -243,6 +245,7 @@ struct sde_encoder_phys_cmd { int stream_sel; int irq_idx[INTR_IDX_MAX]; struct sde_irq_callback irq_cb[INTR_IDX_MAX]; bool serialize_wait4pp; }; /** Loading
drivers/gpu/drm/msm/sde/sde_encoder_phys_cmd.c +20 −12 Original line number Diff line number Diff line Loading @@ -591,18 +591,6 @@ static void sde_encoder_phys_cmd_get_hw_resources( hw_res->intfs[cmd_enc->intf_idx - INTF_0] = INTF_MODE_CMD; } static int sde_encoder_phys_cmd_wait_for_commit_done( struct sde_encoder_phys *phys_enc) { /* * Since ctl_start "commits" the transaction to hardware, and the * tearcheck block takes it from there, there is no need to have a * separate wait for committed, a la wait-for-vsync in video mode */ return 0; } static void sde_encoder_phys_cmd_prepare_for_kickoff( struct sde_encoder_phys *phys_enc) { Loading Loading @@ -631,6 +619,26 @@ static void sde_encoder_phys_cmd_prepare_for_kickoff( } } static int sde_encoder_phys_cmd_wait_for_commit_done( struct sde_encoder_phys *phys_enc) { struct sde_encoder_phys_cmd *cmd_enc = to_sde_encoder_phys_cmd(phys_enc); if (cmd_enc->serialize_wait4pp) sde_encoder_phys_cmd_prepare_for_kickoff(phys_enc); /* * following statement is true serialize_wait4pp is false. * * Since ctl_start "commits" the transaction to hardware, and the * tearcheck block takes it from there, there is no need to have a * separate wait for committed, a la wait-for-vsync in video mode */ return 0; } static void sde_encoder_phys_cmd_init_ops( struct sde_encoder_phys_ops *ops) { Loading