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Commit 9cc58712 authored by Zidan Wang's avatar Zidan Wang Committed by Mark Brown
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ASoC: fsl-sai: don't set bclk for Tx/Rx Synchronous with another SAI mode 



In fsl_sai_set_bclk function, we should not set bclk for Tx/Rx Synchronous
with another SAI mode.

Signed-off-by: default avatarZidan Wang <zidan.wang@freescale.com>
Acked-by: default avatarNicolin Chen <nicoleotsuka@gmail.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 8005c49d

sound/soc/fsl/fsl_sai.c

+14 −2
Original line number Diff line number Diff line
@@ -354,13 +354,25 @@ static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq) 
		return -EINVAL;

	}



	if ((tx && sai->synchronous[TX]) || (!tx && !sai->synchronous[RX])) {

	/*

	 * 1) For Asynchronous mode, we must set RCR2 register for capture, and

	 *    set TCR2 register for playback.

	 * 2) For Tx sync with Rx clock, we must set RCR2 register for playback

	 *    and capture.

	 * 3) For Rx sync with Tx clock, we must set TCR2 register for playback

	 *    and capture.

	 * 4) For Tx and Rx are both Synchronous with another SAI, we just

	 *    ignore it.

	 */

	if ((sai->synchronous[TX] && !sai->synchronous[RX]) ||

	    (!tx && !sai->synchronous[RX])) {

		regmap_update_bits(sai->regmap, FSL_SAI_RCR2,

				   FSL_SAI_CR2_MSEL_MASK,

				   FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));

		regmap_update_bits(sai->regmap, FSL_SAI_RCR2,

				   FSL_SAI_CR2_DIV_MASK, savediv - 1);

	} else {

	} else if ((sai->synchronous[RX] && !sai->synchronous[TX]) ||

		   (tx && !sai->synchronous[TX])) {

		regmap_update_bits(sai->regmap, FSL_SAI_TCR2,

				   FSL_SAI_CR2_MSEL_MASK,

				   FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));