ARM: dts: msm: Add coresight support for sdxpoorwills (9c7f4181) · Commits · e / devices / android_kernel_fairphone_FP3

arch/arm/boot/dts/qcom/sdxpoorwills-coresight.dtsi

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		/* Copyright (c) 2018, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		* only version 2 as published by the Free Software Foundation.
		*
		* This program is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*/

		&soc {
		csr: csr@6001000 {
		compatible = "qcom,coresight-csr";
		reg = <0x6001000 0x1000>;
		reg-names = "csr-base";

		coresight-name = "coresight-csr";

		qcom,blk-size = <1>;
		};

		tmc_etr: tmc@6048000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b961>;

		reg = <0x6048000 0x1000>,
		<0x6064000 0x15000>;
		reg-names = "tmc-base", "bam-base";

		arm,buffer-size = <0x400000>;
		arm,sg-enable;

		coresight-name = "coresight-tmc-etr";
		coresight-ctis = <&cti0 &cti8>;

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		interrupts = <GIC_SPI 251 IRQ_TYPE_EDGE_RISING>;
		interrupt-names = "byte-cntr-irq";

		port {
		tmc_etr_in_replicator: endpoint {
		slave-mode;
		remote-endpoint = <&replicator_out_tmc_etr>;
		};
		};
		};

		replicator_qdss: replicator@6046000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b909>;

		reg = <0x6046000 0x1000>;
		reg-names = "replicator-base";

		coresight-name = "coresight-replicator";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
		reg = <0>;
		replicator_out_tmc_etr: endpoint {
		remote-endpoint=
		<&tmc_etr_in_replicator>;
		};
		};

		port@1 {
		reg = <0>;
		replicator_in_tmc_etf: endpoint {
		slave-mode;
		remote-endpoint=
		<&tmc_etf_out_replicator>;
		};
		};
		};
		};

		tmc_etf: tmc@6047000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b961>;

		reg = <0x6047000 0x1000>;
		reg-names = "tmc-base";

		coresight-name = "coresight-tmc-etf";
		coresight-ctis = <&cti0 &cti8>;
		arm,default-sink;

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
		reg = <0>;
		tmc_etf_out_replicator: endpoint {
		remote-endpoint =
		<&replicator_in_tmc_etf>;
		};
		};

		port@1 {
		reg = <0>;
		tmc_etf_in_funnel_merg: endpoint {
		slave-mode;
		remote-endpoint =
		<&funnel_merg_out_tmc_etf>;
		};
		};
		};
		};

		funnel_merg: funnel@6045000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b908>;

		reg = <0x6045000 0x1000>;
		reg-names = "funnel-base";

		coresight-name = "coresight-funnel-merg";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
		reg = <0>;
		funnel_merg_out_tmc_etf: endpoint {
		remote-endpoint =
		<&tmc_etf_in_funnel_merg>;
		};
		};

		port@1 {
		reg = <0>;
		funnel_merg_in_funnel_in0: endpoint {
		slave-mode;
		remote-endpoint =
		<&funnel_in0_out_funnel_merg>;
		};
		};

		port@2 {
		reg = <1>;
		funnel_merg_in_funnel_in1: endpoint {
		slave-mode;
		remote-endpoint =
		<&funnel_in1_out_funnel_merg>;
		};
		};
		};
		};

		funnel_in0: funnel@6041000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b908>;

		reg = <0x6041000 0x1000>;
		reg-names = "funnel-base";

		coresight-name = "coresight-funnel-in0";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
		reg = <0>;
		funnel_in0_out_funnel_merg: endpoint {
		remote-endpoint =
		<&funnel_merg_in_funnel_in0>;
		};
		};

		port@1 {
		reg = <6>;
		funnel_in0_in_funnel_qatb: endpoint {
		slave-mode;
		remote-endpoint =
		<&funnel_qatb_out_funnel_in0>;
		};
		};

		port@2 {
		reg = <7>;
		funnel_in0_in_stm: endpoint {
		slave-mode;
		remote-endpoint = <&stm_out_funnel_in0>;
		};
		};
		};
		};

		stm: stm@6002000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b962>;

		reg = <0x6002000 0x1000>,
		<0x16280000 0x180000>;
		reg-names = "stm-base", "stm-stimulus-base";

		coresight-name = "coresight-stm";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
		stm_out_funnel_in0: endpoint {
		remote-endpoint = <&funnel_in0_in_stm>;
		};
		};

		};

		funnel_qatb: funnel@6005000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b908>;

		reg = <0x6005000 0x1000>;
		reg-names = "funnel-base";

		coresight-name = "coresight-funnel-qatb";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
		reg = <0>;
		funnel_qatb_out_funnel_in0: endpoint {
		remote-endpoint =
		<&funnel_in0_in_funnel_qatb>;
		};
		};

		port@1 {
		reg = <0>;
		funnel_qatb_in_tpda: endpoint {
		slave-mode;
		remote-endpoint =
		<&tpda_out_funnel_qatb>;
		};
		};
		};
		};

		tpda: tpda@6004000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b969>;
		reg = <0x6004000 0x1000>;
		reg-names = "tpda-base";

		coresight-name = "coresight-tpda";

		qcom,tpda-atid = <65>;
		qcom,bc-elem-size = <10 32>,
		<13 32>;
		qcom,tc-elem-size = <13 32>;
		qcom,dsb-elem-size = <0 32>,
		<2 32>,
		<3 32>,
		<5 32>,
		<6 32>,
		<10 32>,
		<11 32>,
		<13 32>;
		qcom,cmb-elem-size = <3 64>,
		<7 64>,
		<9 64>,
		<13 64>;

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
		#address-cells = <1>;
		#size-cells = <0>;
		port@0 {
		reg = <0>;
		tpda_out_funnel_qatb: endpoint {
		remote-endpoint =
		<&funnel_qatb_in_tpda>;
		};

		};

		port@1 {
		reg = <0>;
		tpda_in_funnel_ddr_0: endpoint {
		slave-mode;
		remote-endpoint =
		<&funnel_ddr_0_out_tpda>;
		};
		};

		port@2 {
		reg = <1>;
		tpda_in_tpdm_vsense: endpoint {
		slave-mode;
		remote-endpoint =
		<&tpdm_vsense_out_tpda>;
		};
		};

		port@3 {
		reg = <2>;
		tpda_in_tpdm_dcc: endpoint {
		slave-mode;
		remote-endpoint =
		<&tpdm_dcc_out_tpda>;
		};
		};

		port@4 {
		reg = <5>;
		tpda_in_tpdm_center: endpoint {
		slave-mode;
		remote-endpoint =
		<&tpdm_center_out_tpda>;
		};
		};
		};
		};

		funnel_ddr_0: funnel@69e2000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b908>;

		reg = <0x69e2000 0x1000>;
		reg-names = "funnel-base";

		coresight-name = "coresight-funnel-ddr-0";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
		reg = <0>;
		funnel_ddr_0_out_tpda: endpoint {
		remote-endpoint =
		<&tpda_in_funnel_ddr_0>;
		};
		};

		port@1 {
		reg = <0>;
		funnel_ddr_0_in_tpdm_ddr: endpoint {
		slave-mode;
		remote-endpoint =
		<&tpdm_ddr_out_funnel_ddr_0>;
		};
		};
		};
		};

		tpdm_dcc: tpdm@6870280 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b968>;
		reg = <0x6870280 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-dcc";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		port{
		tpdm_dcc_out_tpda: endpoint {
		remote-endpoint = <&tpda_in_tpdm_dcc>;
		};
		};
		};

		tpdm_vsense: tpdm@6840000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b968>;
		reg = <0x6840000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-vsense";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		port{
		tpdm_vsense_out_tpda: endpoint {
		remote-endpoint = <&tpda_in_tpdm_vsense>;
		};
		};
		};

		tpdm_center: tpdm@6c28000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b968>;
		reg = <0x6c28000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-center";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		port{
		tpdm_center_out_tpda: endpoint {
		remote-endpoint = <&tpda_in_tpdm_center>;
		};
		};
		};

		tpdm_ddr: tpdm@69e0000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b968>;
		reg = <0x69e0000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-ddr";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		qcom,msr-fix-req;

		port {
		tpdm_ddr_out_funnel_ddr_0: endpoint {
		remote-endpoint = <&funnel_ddr_0_in_tpdm_ddr>;
		};
		};
		};

		funnel_in1: funnel@6042000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b908>;

		reg = <0x6042000 0x1000>;
		reg-names = "funnel-base";

		coresight-name = "coresight-funnel-in1";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
		reg = <0>;
		funnel_in1_out_funnel_merg: endpoint {
		remote-endpoint =
		<&funnel_merg_in_funnel_in1>;
		};
		};

		port@1 {
		reg = <2>;
		funnel_in1_in_funnel_swao: endpoint {
		slave-mode;
		remote-endpoint =
		<&funnel_swao_out_funnel_in1>;
		};
		};

		port@2 {
		reg = <3>;
		funnel_in1_in_modem_etm0: endpoint {
		slave-mode;
		remote-endpoint =
		<&modem_etm0_out_funnel_in1>;
		};
		};

		port@3 {
		reg = <7>;
		funnel_in1_in_tpda_modem: endpoint {
		slave-mode;
		remote-endpoint =
		<&tpda_modem_out_funnel_in1>;
		};
		};
		};
		};

		modem_etm0 {
		compatible = "qcom,coresight-remote-etm";

		coresight-name = "coresight-modem-etm0";
		qcom,inst-id = <2>;

		port {
		modem_etm0_out_funnel_in1: endpoint {
		remote-endpoint =
		<&funnel_in1_in_modem_etm0>;
		};
		};
		};

		funnel_swao:funnel@6b08000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b908>;

		reg = <0x6b08000 0x1000>;
		reg-names = "funnel-base";

		coresight-name = "coresight-funnel-swao";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
		reg = <0>;
		funnel_swao_out_funnel_in1: endpoint {
		remote-endpoint =
		<&funnel_in1_in_funnel_swao>;
		};
		};

		port@1 {
		reg = <7>;
		funnel_swao_in_tpda_swao: endpoint {
		slave-mode;
		remote-endpoint=
		<&tpda_swao_out_funnel_swao>;
		};
		};
		};
		};

		tpda_modem: tpda@6832000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b969>;
		reg = <0x6832000 0x1000>;
		reg-names = "tpda-base";

		coresight-name = "coresight-tpda-modem";

		qcom,tpda-atid = <67>;
		qcom,dsb-elem-size = <0 32>;
		qcom,cmb-elem-size = <0 64>;

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
		#address-cells = <1>;
		#size-cells = <0>;
		port@0 {
		reg = <0>;
		tpda_modem_out_funnel_in1: endpoint {
		remote-endpoint =
		<&funnel_in1_in_tpda_modem>;
		};
		};

		port@1 {
		reg = <0>;
		tpda_modem_in_tpdm_modem: endpoint {
		slave-mode;
		remote-endpoint =
		<&tpdm_modem_out_tpda_modem>;
		};
		};
		};
		};

		tpdm_modem: tpdm@6830000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b968>;
		reg = <0x6830000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-modem";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
		tpdm_modem_out_tpda_modem: endpoint {
		remote-endpoint = <&tpda_modem_in_tpdm_modem>;
		};
		};
		};

		tpda_swao: tpda@6b01000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b969>;
		reg = <0x6b01000 0x1000>;
		reg-names = "tpda-base";

		coresight-name = "coresight-tpda-swao";

		qcom,tpda-atid = <71>;
		qcom,dsb-elem-size = <1 32>;
		qcom,cmb-elem-size = <0 64>;

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
		reg = <0>;
		tpda_swao_out_funnel_swao: endpoint {
		remote-endpoint =
		<&funnel_swao_in_tpda_swao>;
		};

		};

		port@1 {
		reg = <0>;
		tpda_swao_in_tpdm_swao0: endpoint {
		slave-mode;
		remote-endpoint =
		<&tpdm_swao0_out_tpda_swao>;
		};
		};

		port@2 {
		reg = <1>;
		tpda_swao_in_tpdm_swao1: endpoint {
		slave-mode;
		remote-endpoint =
		<&tpdm_swao1_out_tpda_swao>;
		};

		};
		};
		};

		tpdm_swao0: tpdm@6b02000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b968>;

		reg = <0x6b02000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-swao-0";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
		tpdm_swao0_out_tpda_swao: endpoint {
		remote-endpoint = <&tpda_swao_in_tpdm_swao0>;
		};
		};
		};

		tpdm_swao1: tpdm@6b03000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b968>;
		reg = <0x6b03000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name="coresight-tpdm-swao-1";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		qcom,msr-fix-req;

		port {
		tpdm_swao1_out_tpda_swao: endpoint {
		remote-endpoint = <&tpda_swao_in_tpdm_swao1>;
		};
		};
		};

		ipcb_tgu: tgu@6b0c000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b999>;
		reg = <0x6b0c000 0x1000>;
		reg-names = "tgu-base";
		tgu-steps = <3>;
		tgu-conditions = <4>;
		tgu-regs = <4>;
		tgu-timer-counters = <8>;

		coresight-name = "coresight-tgu-ipcb";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
		};

		cti0: cti@6010000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6010000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti0";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		};

		cti1: cti@6011000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6011000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti1";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		};

		cti2: cti@6012000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6012000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti2";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
		};

		cti3: cti@6013000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6013000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti3";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		};

		cti4: cti@6014000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6014000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti4";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		};

		cti5: cti@6015000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6015000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti5";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		};

		cti6: cti@6016000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6016000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti6";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		};

		cti7: cti@6017000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6017000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti7";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		};

		cti8: cti@6018000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6018000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti8";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		};

		cti9: cti@6019000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6019000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti9";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		};

		cti10: cti@601a000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x601a000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti10";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		};

		cti11: cti@601b000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x601b000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti11";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		};

		cti12: cti@601c000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x601c000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti12";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		};

		cti13: cti@601d000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x601d000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti13";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		};

		cti14: cti@601e000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x601e000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti14";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		};

		cti15: cti@601f000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x601f000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti15";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		};

		cti_cpu0: cti@7003000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x7003000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-cpu0";
		cpu = <&CPU0>;

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		};

		cti_modem_cpu0:cti@6837000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6837000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-modem-cpu0";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
		};

		cti_modem_cpu1:cti@683b000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x683b000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-modem-cpu1";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
		};

		cti0_swao:cti@6b04000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6b04000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-swao_cti0";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
		};

		cti1_swao:cti@6b05000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6b05000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-swao_cti1";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
		};

		cti2_swao:cti@6b06000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6b06000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-swao_cti2";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
		};

		cti3_swao:cti@6b07000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6b07000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-swao_cti3";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
		};

		cti0_ddr0: cti@69e1000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x69e1000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-ddr_dl_0_cti";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
		};

		cti0_ddr1: cti@69e4000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x69e4000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-ddr_dl_1_cti0";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
		};

		cti1_ddr1: cti@69e5000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x69e5000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-ddr_dl_1_cti1";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
		};

		cti2_ddr1: cti@69e6000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x69e6000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-ddr_dl_1_cti2";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
		};

		hwevent: hwevent@0x014066f0 {
		compatible = "qcom,coresight-hwevent";
		reg = <0x14066f0 0x4>,
		<0x14166f0 0x4>,
		<0x1406038 0x4>,
		<0x1416038 0x4>;
		reg-names = "ddr-ch0-cfg", "ddr-ch23-cfg", "ddr-ch0-ctrl",
		"ddr-ch23-ctrl";

		coresight-name = "coresight-hwevent";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
		};
		};

arch/arm/boot/dts/qcom/sdxpoorwills.dtsi

+1 −0

Original line number	Diff line number	Diff line
		@@ -804,6 +804,7 @@
		#include "sdxpoorwills-audio.dtsi"
		#include "sdxpoorwills-ion.dtsi"
		#include "msm-arm-smmu-sdxpoorwills.dtsi"
		#include "sdxpoorwills-coresight.dtsi"

		&soc {
		emac_hw: qcom,emac@00020000 {