Merge "ARM: dts: msm: create PCIe Gen3 node for sdm845" (9c713888) · Commits · e / devices / android_kernel_fairphone_FP3

Documentation/devicetree/bindings/pci/msm_pcie.txt

+4 −0

Original line number	Diff line number	Diff line
		@@ -70,6 +70,7 @@ Optional Properties:
		- qcom,common-clk-en: Enables the common clock configuration for the endpoint.
		- qcom,clk-power-manage-en: Enables the clock power management for the
		endpoint.
		- qcom,max-link-speed: Max Gen speed Root complex supports.
		- qcom,n-fts: The number of fast training sequences sent when the link state
		is changed from L0s to L0.
		- qcom,pcie-phy-ver: version of PCIe PHY.
		@@ -96,6 +97,7 @@ Optional Properties:
		stable after power on, before de-assert the PERST to the endpoint.
		- qcom,wr-halt-size: With base 2, this exponent determines the size of the
		data that PCIe core will halt on for each write transaction.
		- qcom,slv-addr-space-size: The memory space size of PCIe Root Complex.
		- qcom,cpl-timeout: Completion timeout value. This value specifies the time range
		which the root complex will send out a completion packet if there is no response
		from the endpoint.
		@@ -255,6 +257,7 @@ Example:
		qcom,l1-supported;
		qcom,l1ss-supported;
		qcom,aux-clk-sync;
		qcom,max-link-speed = <0x2>;
		qcom,n-fts = <0x50>;
		qcom,pcie-phy-ver = <1>;
		qcom,boot-option = <0x1>;
		@@ -266,6 +269,7 @@ Example:
		qcom,smmu-sid-base = <0x1480>;
		qcom,ep-latency = <100>;
		qcom,wr-halt-size = <0xa>; /* 1KB */
		qcom,slv-addr-space-size = <0x1000000>; /* 16MB */
		qcom,cpl-timeout = <0x2>;

		iommus = <&anoc0_smmu>;

arch/arm64/boot/dts/qcom/sdm845-interposer-pm660.dtsi

+6 −0

Original line number	Diff line number	Diff line
		@@ -129,6 +129,12 @@
		/delete-property/ vreg-cx-supply;
		};

		&pcie1 {
		/delete-property/ vreg-1.8-supply;
		/delete-property/ vreg-0.9-supply;
		/delete-property/ vreg-cx-supply;
		};

		&cam_csiphy0 {
		/delete-property/ mipi-csi-vdd-supply;
		};

arch/arm64/boot/dts/qcom/sdm845-pcie.dtsi

+333 −0

Original line number	Diff line number	Diff line
		@@ -265,4 +265,337 @@
		reset-names = "pcie_0_core_reset",
		"pcie_0_phy_reset";
		};

		pcie1: qcom,pcie@0x1c08000 {
		compatible = "qcom,pci-msm";
		cell-index = <1>;

		reg = <0x1c08000 0x2000>,
		<0x1c0a000 0x2000>,
		<0x40000000 0xf1d>,
		<0x40000f20 0xa8>,
		<0x40100000 0x100000>,
		<0x40200000 0x100000>,
		<0x40300000 0x1fd00000>;

		reg-names = "parf", "phy", "dm_core", "elbi",
		"conf", "io", "bars";

		#address-cells = <3>;
		#size-cells = <2>;
		ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>,
		<0x02000000 0x0 0x40300000 0x40300000 0x0 0x1fd00000>;
		interrupt-parent = <&pcie1>;
		interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
		20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
		36 37>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0xffffffff>;
		interrupt-map = <0 0 0 0 &intc 0 307 0
		0 0 0 1 &intc 0 434 0
		0 0 0 2 &intc 0 435 0
		0 0 0 3 &intc 0 438 0
		0 0 0 4 &intc 0 439 0
		0 0 0 5 &intc 0 306 0
		0 0 0 6 &intc 0 704 0
		0 0 0 7 &intc 0 705 0
		0 0 0 8 &intc 0 706 0
		0 0 0 9 &intc 0 707 0
		0 0 0 10 &intc 0 708 0
		0 0 0 11 &intc 0 709 0
		0 0 0 12 &intc 0 710 0
		0 0 0 13 &intc 0 711 0
		0 0 0 14 &intc 0 712 0
		0 0 0 15 &intc 0 713 0
		0 0 0 16 &intc 0 714 0
		0 0 0 17 &intc 0 715 0
		0 0 0 18 &intc 0 716 0
		0 0 0 19 &intc 0 717 0
		0 0 0 20 &intc 0 718 0
		0 0 0 21 &intc 0 719 0
		0 0 0 22 &intc 0 720 0
		0 0 0 23 &intc 0 721 0
		0 0 0 24 &intc 0 722 0
		0 0 0 25 &intc 0 723 0
		0 0 0 26 &intc 0 724 0
		0 0 0 27 &intc 0 725 0
		0 0 0 28 &intc 0 726 0
		0 0 0 29 &intc 0 727 0
		0 0 0 30 &intc 0 728 0
		0 0 0 31 &intc 0 729 0
		0 0 0 32 &intc 0 730 0
		0 0 0 33 &intc 0 731 0
		0 0 0 34 &intc 0 732 0
		0 0 0 35 &intc 0 733 0
		0 0 0 36 &intc 0 734 0
		0 0 0 37 &intc 0 735 0>;

		interrupt-names = "int_msi", "int_a", "int_b", "int_c",
		"int_d", "int_global_int",
		"msi_0", "msi_1", "msi_2", "msi_3",
		"msi_4", "msi_5", "msi_6", "msi_7",
		"msi_8", "msi_9", "msi_10", "msi_11",
		"msi_12", "msi_13", "msi_14", "msi_15",
		"msi_16", "msi_17", "msi_18", "msi_19",
		"msi_20", "msi_21", "msi_22", "msi_23",
		"msi_24", "msi_25", "msi_26", "msi_27",
		"msi_28", "msi_29", "msi_30", "msi_31";

		qcom,phy-sequence = <0x1804 0x03 0x0
		0x00dc 0x27 0x0
		0x0014 0x01 0x0
		0x0020 0x31 0x0
		0x0024 0x01 0x0
		0x0028 0xde 0x0
		0x002c 0x07 0x0
		0x0034 0x4c 0x0
		0x0038 0x06 0x0
		0x0054 0x18 0x0
		0x0058 0xb0 0x0
		0x006c 0x8c 0x0
		0x0070 0x20 0x0
		0x0078 0x14 0x0
		0x007c 0x34 0x0
		0x00b4 0x06 0x0
		0x00b8 0x06 0x0
		0x00c0 0x16 0x0
		0x00c4 0x16 0x0
		0x00cc 0x36 0x0
		0x00d0 0x36 0x0
		0x00f0 0x05 0x0
		0x00f8 0x42 0x0
		0x0100 0x82 0x0
		0x0108 0x68 0x0
		0x011c 0x55 0x0
		0x0120 0x55 0x0
		0x0124 0x03 0x0
		0x0128 0xab 0x0
		0x012c 0xaa 0x0
		0x0130 0x02 0x0
		0x0150 0x3f 0x0
		0x0158 0x3f 0x0
		0x0178 0x10 0x0
		0x01cc 0x04 0x0
		0x01d0 0x30 0x0
		0x01e0 0x04 0x0
		0x01e8 0x73 0x0
		0x01f0 0x1c 0x0
		0x01fc 0x15 0x0
		0x021c 0x04 0x0
		0x0224 0x01 0x0
		0x0228 0x22 0x0
		0x022c 0x00 0x0
		0x0098 0x05 0x0
		0x080c 0x00 0x0
		0x0818 0x0d 0x0
		0x0860 0x01 0x0
		0x0864 0x3a 0x0
		0x087c 0x2f 0x0
		0x08c0 0x09 0x0
		0x08c4 0x09 0x0
		0x08c8 0x1a 0x0
		0x08d0 0x01 0x0
		0x08d4 0x07 0x0
		0x08d8 0x31 0x0
		0x08dc 0x31 0x0
		0x08e0 0x03 0x0
		0x08fc 0x02 0x0
		0x0900 0x01 0x0
		0x0908 0x12 0x0
		0x0914 0x25 0x0
		0x0918 0x00 0x0
		0x091c 0x05 0x0
		0x0920 0x01 0x0
		0x0924 0x26 0x0
		0x0928 0x12 0x0
		0x0930 0x04 0x0
		0x0934 0x04 0x0
		0x0938 0x09 0x0
		0x0954 0x15 0x0
		0x0960 0x32 0x0
		0x0968 0x7f 0x0
		0x096c 0x07 0x0
		0x0978 0x04 0x0
		0x0980 0x70 0x0
		0x0984 0x8b 0x0
		0x0988 0x08 0x0
		0x098c 0x09 0x0
		0x0990 0x03 0x0
		0x0994 0x04 0x0
		0x0998 0x02 0x0
		0x099c 0x0c 0x0
		0x09a4 0x02 0x0
		0x09c0 0x5c 0x0
		0x09c4 0x3e 0x0
		0x09c8 0x3f 0x0
		0x0a30 0x01 0x0
		0x0a34 0xa0 0x0
		0x0a38 0x08 0x0
		0x0aa4 0x01 0x0
		0x0aac 0xc3 0x0
		0x0ab0 0x00 0x0
		0x0ab8 0x8c 0x0
		0x0ac0 0x7f 0x0
		0x0ac4 0x2a 0x0
		0x0810 0x0c 0x0
		0x0814 0x00 0x0
		0x0acc 0x04 0x0
		0x093c 0x20 0x0
		0x100c 0x00 0x0
		0x1018 0x0d 0x0
		0x1060 0x01 0x0
		0x1064 0x3a 0x0
		0x107c 0x2f 0x0
		0x10c0 0x09 0x0
		0x10c4 0x09 0x0
		0x10c8 0x1a 0x0
		0x10d0 0x01 0x0
		0x10d4 0x07 0x0
		0x10d8 0x31 0x0
		0x10dc 0x31 0x0
		0x10e0 0x03 0x0
		0x10fc 0x02 0x0
		0x1100 0x01 0x0
		0x1108 0x12 0x0
		0x1114 0x25 0x0
		0x1118 0x00 0x0
		0x111c 0x05 0x0
		0x1120 0x01 0x0
		0x1124 0x26 0x0
		0x1128 0x12 0x0
		0x1130 0x04 0x0
		0x1134 0x04 0x0
		0x1138 0x09 0x0
		0x1154 0x15 0x0
		0x1160 0x32 0x0
		0x1168 0x7f 0x0
		0x116c 0x07 0x0
		0x1178 0x04 0x0
		0x1180 0x70 0x0
		0x1184 0x8b 0x0
		0x1188 0x08 0x0
		0x118c 0x09 0x0
		0x1190 0x03 0x0
		0x1194 0x04 0x0
		0x1198 0x02 0x0
		0x119c 0x0c 0x0
		0x11a4 0x02 0x0
		0x11c0 0x5c 0x0
		0x11c4 0x3e 0x0
		0x11c8 0x3f 0x0
		0x1230 0x01 0x0
		0x1234 0xa0 0x0
		0x1238 0x08 0x0
		0x12a4 0x01 0x0
		0x12ac 0xc3 0x0
		0x12b0 0x00 0x0
		0x12b8 0x8c 0x0
		0x12c0 0x7f 0x0
		0x12c4 0x2a 0x0
		0x1010 0x0c 0x0
		0x1014 0x00 0x0
		0x12cc 0x04 0x0
		0x113c 0x20 0x0
		0x195c 0x3f 0x0
		0x1974 0x58 0x0
		0x196c 0x9f 0x0
		0x182c 0x19 0x0
		0x1840 0x07 0x0
		0x1854 0x17 0x0
		0x1868 0x09 0x0
		0x1800 0x00 0x0
		0x0aa8 0x01 0x0
		0x12a8 0x01 0x0
		0x1808 0x01 0x0>;

		pinctrl-names = "default";
		pinctrl-0 = <&pcie1_clkreq_default
		&pcie1_perst_default
		&pcie1_wake_default>;

		perst-gpio = <&tlmm 102 0>;
		wake-gpio = <&tlmm 104 0>;

		gdsc-vdd-supply = <&pcie_1_gdsc>;
		vreg-1.8-supply = <&pm8998_l26>;
		vreg-0.9-supply = <&pm8998_l1>;
		vreg-cx-supply = <&pm8998_s9_level>;

		qcom,vreg-1.8-voltage-level = <1200000 1200000 24000>;
		qcom,vreg-0.9-voltage-level = <880000 880000 24000>;
		qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
		RPMH_REGULATOR_LEVEL_NOM 0>;

		qcom,l1-supported;
		qcom,l1ss-supported;
		qcom,aux-clk-sync;

		qcom,ep-latency = <10>;

		qcom,slv-addr-space-size = <0x20000000>;

		qcom,boot-option = <0x1>;

		linux,pci-domain = <1>;

		qcom,msi-gicm-addr = <0x17a00040>;
		qcom,msi-gicm-base = <0x2e0>;

		qcom,max-link-speed = <0x3>;

		qcom,use-19p2mhz-aux-clk;

		qcom,smmu-sid-base = <0x1c00>;

		iommu-map = <0x100 &apps_smmu 0x1c01 0x1>,
		<0x200 &apps_smmu 0x1c02 0x1>,
		<0x300 &apps_smmu 0x1c03 0x1>,
		<0x400 &apps_smmu 0x1c04 0x1>,
		<0x500 &apps_smmu 0x1c05 0x1>,
		<0x600 &apps_smmu 0x1c06 0x1>,
		<0x700 &apps_smmu 0x1c07 0x1>,
		<0x800 &apps_smmu 0x1c08 0x1>,
		<0x900 &apps_smmu 0x1c09 0x1>,
		<0xa00 &apps_smmu 0x1c0a 0x1>,
		<0xb00 &apps_smmu 0x1c0b 0x1>,
		<0xc00 &apps_smmu 0x1c0c 0x1>,
		<0xd00 &apps_smmu 0x1c0d 0x1>,
		<0xe00 &apps_smmu 0x1c0e 0x1>,
		<0xf00 &apps_smmu 0x1c0f 0x1>;

		qcom,msm-bus,name = "pcie1";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
		<100 512 0 0>,
		<100 512 500 800>;

		clocks = <&clock_gcc GCC_PCIE_1_PIPE_CLK>,
		<&clock_rpmh RPMH_CXO_CLK>,
		<&clock_gcc GCC_PCIE_1_AUX_CLK>,
		<&clock_gcc GCC_PCIE_1_CFG_AHB_CLK>,
		<&clock_gcc GCC_PCIE_1_MSTR_AXI_CLK>,
		<&clock_gcc GCC_PCIE_1_SLV_AXI_CLK>,
		<&clock_gcc GCC_PCIE_1_CLKREF_CLK>,
		<&clock_gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
		<&clock_gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
		<&clock_gcc GCC_PCIE_PHY_REFGEN_CLK>,
		<&clock_gcc GCC_PCIE_PHY_AUX_CLK>;

		clock-names = "pcie_1_pipe_clk", "pcie_1_ref_clk_src",
		"pcie_1_aux_clk", "pcie_1_cfg_ahb_clk",
		"pcie_1_mstr_axi_clk", "pcie_1_slv_axi_clk",
		"pcie_1_ldo", "pcie_1_slv_q2a_axi_clk",
		"pcie_tbu_clk", "pcie_phy_refgen_clk",
		"pcie_phy_aux_clk";

		max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>,
		<0>, <0>, <0>, <0>, <100000000>, <0>;

		resets = <&clock_gcc GCC_PCIE_1_BCR>,
		<&clock_gcc GCC_PCIE_1_PHY_BCR>;

		reset-names = "pcie_1_core_reset",
		"pcie_1_phy_reset";
		};
		};

arch/arm64/boot/dts/qcom/sdm845-pinctrl.dtsi

+41 −0

Original line number	Diff line number	Diff line
		@@ -215,6 +215,47 @@
		};
		};

		pcie1 {
		pcie1_clkreq_default: pcie1_clkreq_default {
		mux {
		pins = "gpio103";
		function = "pci_e1";
		};

		config {
		pins = "gpio103";
		drive-strength = <2>;
		bias-pull-up;
		};
		};

		pcie1_perst_default: pcie1_perst_default {
		mux {
		pins = "gpio102";
		function = "gpio";
		};

		config {
		pins = "gpio102";
		drive-strength = <2>;
		bias-pull-down;
		};
		};

		pcie1_wake_default: pcie1_wake_default {
		mux {
		pins = "gpio104";
		function = "gpio";
		};

		config {
		pins = "gpio104";
		drive-strength = <2>;
		bias-pull-down;
		};
		};
		};

		cdc_reset_ctrl {
		cdc_reset_sleep: cdc_reset_sleep {
		mux {

arch/arm64/boot/dts/qcom/sdm845.dtsi

+1 −0

Original line number	Diff line number	Diff line
		@@ -36,6 +36,7 @@
		ufshc1 = &ufshc_mem; /* Embedded UFS slot */
		ufshc2 = &ufshc_card; /* Removable UFS slot */
		pci-domain0 = &pcie0;
		pci-domain1 = &pcie1;
		sdhc2 = &sdhc_2; /* SDC2 SD card slot */
		};