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Commit 9c68ed09 authored by Anish Bhatt's avatar Anish Bhatt Committed by Greg Kroah-Hartman
Browse files

rtl8188eu : BIT() macro cleanup 



Use the BIT(x) macro directly instead using multiple
BITX defines.

Signed-off-by: default avatarAnish Bhatt <anish@gatech.edu>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent b0dcce5f

drivers/staging/rtl8188eu/core/rtw_efuse.c

+24 −24
Original line number Diff line number Diff line
@@ -396,7 +396,7 @@ u8 Efuse_WordEnableDataWrite(struct adapter *pAdapter, u16 efuse_addr, u8 word_e 


	memset((void *)tmpdata, 0xff, PGPKT_DATA_SIZE);



	if (!(word_en&BIT0)) {

	if (!(word_en & BIT(0))) {

		tmpaddr = start_addr;

		efuse_OneByteWrite(pAdapter, start_addr++, data[0]);

		efuse_OneByteWrite(pAdapter, start_addr++, data[1]);
@@ -404,9 +404,9 @@ u8 Efuse_WordEnableDataWrite(struct adapter *pAdapter, u16 efuse_addr, u8 word_e 
		efuse_OneByteRead(pAdapter, tmpaddr, &tmpdata[0]);

		efuse_OneByteRead(pAdapter, tmpaddr+1, &tmpdata[1]);

		if ((data[0] != tmpdata[0]) || (data[1] != tmpdata[1]))

			badworden &= (~BIT0);

			badworden &= (~BIT(0));

	}

	if (!(word_en&BIT1)) {

	if (!(word_en & BIT(1))) {

		tmpaddr = start_addr;

		efuse_OneByteWrite(pAdapter, start_addr++, data[2]);

		efuse_OneByteWrite(pAdapter, start_addr++, data[3]);
@@ -414,9 +414,9 @@ u8 Efuse_WordEnableDataWrite(struct adapter *pAdapter, u16 efuse_addr, u8 word_e 
		efuse_OneByteRead(pAdapter, tmpaddr, &tmpdata[2]);

		efuse_OneByteRead(pAdapter, tmpaddr+1, &tmpdata[3]);

		if ((data[2] != tmpdata[2]) || (data[3] != tmpdata[3]))

			badworden &= (~BIT1);

			badworden &= (~BIT(1));

	}

	if (!(word_en&BIT2)) {

	if (!(word_en & BIT(2))) {

		tmpaddr = start_addr;

		efuse_OneByteWrite(pAdapter, start_addr++, data[4]);

		efuse_OneByteWrite(pAdapter, start_addr++, data[5]);
@@ -424,9 +424,9 @@ u8 Efuse_WordEnableDataWrite(struct adapter *pAdapter, u16 efuse_addr, u8 word_e 
		efuse_OneByteRead(pAdapter, tmpaddr, &tmpdata[4]);

		efuse_OneByteRead(pAdapter, tmpaddr+1, &tmpdata[5]);

		if ((data[4] != tmpdata[4]) || (data[5] != tmpdata[5]))

			badworden &= (~BIT2);

			badworden &= (~BIT(2));

	}

	if (!(word_en&BIT3)) {

	if (!(word_en & BIT(3))) {

		tmpaddr = start_addr;

		efuse_OneByteWrite(pAdapter, start_addr++, data[6]);

		efuse_OneByteWrite(pAdapter, start_addr++, data[7]);
@@ -434,7 +434,7 @@ u8 Efuse_WordEnableDataWrite(struct adapter *pAdapter, u16 efuse_addr, u8 word_e 
		efuse_OneByteRead(pAdapter, tmpaddr, &tmpdata[6]);

		efuse_OneByteRead(pAdapter, tmpaddr+1, &tmpdata[7]);

		if ((data[6] != tmpdata[6]) || (data[7] != tmpdata[7]))

			badworden &= (~BIT3);

			badworden &= (~BIT(3));

	}

	return badworden;

}
@@ -738,18 +738,18 @@ static bool wordEnMatched(struct pgpkt *pTargetPkt, struct pgpkt *pCurPkt, 
	u8 match_word_en = 0x0F;	/*  default all words are disabled */



	/*  check if the same words are enabled both target and current PG packet */

	if (((pTargetPkt->word_en & BIT0) == 0) &&

	    ((pCurPkt->word_en & BIT0) == 0))

		match_word_en &= ~BIT0;				/*  enable word 0 */

	if (((pTargetPkt->word_en & BIT1) == 0) &&

	    ((pCurPkt->word_en & BIT1) == 0))

		match_word_en &= ~BIT1;				/*  enable word 1 */

	if (((pTargetPkt->word_en & BIT2) == 0) &&

	    ((pCurPkt->word_en & BIT2) == 0))

		match_word_en &= ~BIT2;				/*  enable word 2 */

	if (((pTargetPkt->word_en & BIT3) == 0) &&

	    ((pCurPkt->word_en & BIT3) == 0))

		match_word_en &= ~BIT3;				/*  enable word 3 */

	if (((pTargetPkt->word_en & BIT(0)) == 0) &&

	    ((pCurPkt->word_en & BIT(0)) == 0))

		match_word_en &= ~BIT(0);				/*  enable word 0 */

	if (((pTargetPkt->word_en & BIT(1)) == 0) &&

	    ((pCurPkt->word_en & BIT(1)) == 0))

		match_word_en &= ~BIT(1);				/*  enable word 1 */

	if (((pTargetPkt->word_en & BIT(2)) == 0) &&

	    ((pCurPkt->word_en & BIT(2)) == 0))

		match_word_en &= ~BIT(2);				/*  enable word 2 */

	if (((pTargetPkt->word_en & BIT(3)) == 0) &&

	    ((pCurPkt->word_en & BIT(3)) == 0))

		match_word_en &= ~BIT(3);				/*  enable word 3 */



	*pWden = match_word_en;

drivers/staging/rtl8188eu/hal/bb_cfg.c

+1 −1
Original line number Diff line number Diff line
@@ -705,7 +705,7 @@ bool rtl88eu_phy_bb_config(struct adapter *adapt) 


	/*  Enable BB and RF */

	regval = usb_read16(adapt, REG_SYS_FUNC_EN);

	usb_write16(adapt, REG_SYS_FUNC_EN, (u16)(regval|BIT13|BIT0|BIT1));

	usb_write16(adapt, REG_SYS_FUNC_EN, (u16)(regval | BIT(13) | BIT(0) | BIT(1)));



	usb_write8(adapt, REG_RF_CTRL, RF_EN|RF_RSTB|RF_SDMRSTB);

drivers/staging/rtl8188eu/hal/odm.c

+12 −12
Original line number Diff line number Diff line
@@ -437,7 +437,7 @@ void odm_CommonInfoSelfInit(struct odm_dm_struct *pDM_Odm) 
{

	struct adapter *adapter = pDM_Odm->Adapter;



	pDM_Odm->bCckHighPower = (bool)phy_query_bb_reg(adapter, 0x824, BIT9);

	pDM_Odm->bCckHighPower = (bool)phy_query_bb_reg(adapter, 0x824, BIT(9));

	pDM_Odm->RFPathRxEnable = (u8)phy_query_bb_reg(adapter, 0xc04, 0x0F);



	ODM_InitDebugSetting(pDM_Odm);
@@ -736,8 +736,8 @@ void odm_FalseAlarmCounterStatistics(struct odm_dm_struct *pDM_Odm) 
		return;



	/* hold ofdm counter */

	phy_set_bb_reg(adapter, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 1); /* hold page C counter */

	phy_set_bb_reg(adapter, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 1); /* hold page D counter */

	phy_set_bb_reg(adapter, ODM_REG_OFDM_FA_HOLDC_11N, BIT(31), 1); /* hold page C counter */

	phy_set_bb_reg(adapter, ODM_REG_OFDM_FA_RSTD_11N, BIT(31), 1); /* hold page D counter */



	ret_value = phy_query_bb_reg(adapter, ODM_REG_OFDM_FA_TYPE1_11N, bMaskDWord);

	FalseAlmCnt->Cnt_Fast_Fsync = (ret_value&0xffff);
@@ -760,8 +760,8 @@ void odm_FalseAlarmCounterStatistics(struct odm_dm_struct *pDM_Odm) 
	FalseAlmCnt->Cnt_BW_USC = (ret_value & 0xffff0000)>>16;



	/* hold cck counter */

	phy_set_bb_reg(adapter, ODM_REG_CCK_FA_RST_11N, BIT12, 1);

	phy_set_bb_reg(adapter, ODM_REG_CCK_FA_RST_11N, BIT14, 1);

	phy_set_bb_reg(adapter, ODM_REG_CCK_FA_RST_11N, BIT(12), 1);

	phy_set_bb_reg(adapter, ODM_REG_CCK_FA_RST_11N, BIT(14), 1);



	ret_value = phy_query_bb_reg(adapter, ODM_REG_CCK_FA_LSB_11N, bMaskByte0);

	FalseAlmCnt->Cnt_Cck_fail = ret_value;
@@ -853,7 +853,7 @@ void ODM_RF_Saving(struct odm_dm_struct *pDM_Odm, u8 bForceInNormal) 
	}

	if (pDM_PSTable->initialize == 0) {

		pDM_PSTable->Reg874 = (phy_query_bb_reg(adapter, 0x874, bMaskDWord)&0x1CC000)>>14;

		pDM_PSTable->RegC70 = (phy_query_bb_reg(adapter, 0xc70, bMaskDWord)&BIT3)>>3;

		pDM_PSTable->RegC70 = (phy_query_bb_reg(adapter, 0xc70, bMaskDWord) & BIT(3))>>3;

		pDM_PSTable->Reg85C = (phy_query_bb_reg(adapter, 0x85c, bMaskDWord)&0xFF000000)>>24;

		pDM_PSTable->RegA74 = (phy_query_bb_reg(adapter, 0xa74, bMaskDWord)&0xF000)>>12;

		pDM_PSTable->initialize = 1;
@@ -882,18 +882,18 @@ void ODM_RF_Saving(struct odm_dm_struct *pDM_Odm, u8 bForceInNormal) 
	if (pDM_PSTable->PreRFState != pDM_PSTable->CurRFState) {

		if (pDM_PSTable->CurRFState == RF_Save) {

			phy_set_bb_reg(adapter, 0x874, 0x1C0000, 0x2); /* Reg874[20:18]=3'b010 */

			phy_set_bb_reg(adapter, 0xc70, BIT3, 0); /* RegC70[3]=1'b0 */

			phy_set_bb_reg(adapter, 0xc70, BIT(3), 0); /* RegC70[3]=1'b0 */

			phy_set_bb_reg(adapter, 0x85c, 0xFF000000, 0x63); /* Reg85C[31:24]=0x63 */

			phy_set_bb_reg(adapter, 0x874, 0xC000, 0x2); /* Reg874[15:14]=2'b10 */

			phy_set_bb_reg(adapter, 0xa74, 0xF000, 0x3); /* RegA75[7:4]=0x3 */

			phy_set_bb_reg(adapter, 0x818, BIT28, 0x0); /* Reg818[28]=1'b0 */

			phy_set_bb_reg(adapter, 0x818, BIT28, 0x1); /* Reg818[28]=1'b1 */

			phy_set_bb_reg(adapter, 0x818, BIT(28), 0x0); /* Reg818[28]=1'b0 */

			phy_set_bb_reg(adapter, 0x818, BIT(28), 0x1); /* Reg818[28]=1'b1 */

		} else {

			phy_set_bb_reg(adapter, 0x874, 0x1CC000, pDM_PSTable->Reg874);

			phy_set_bb_reg(adapter, 0xc70, BIT3, pDM_PSTable->RegC70);

			phy_set_bb_reg(adapter, 0xc70, BIT(3), pDM_PSTable->RegC70);

			phy_set_bb_reg(adapter, 0x85c, 0xFF000000, pDM_PSTable->Reg85C);

			phy_set_bb_reg(adapter, 0xa74, 0xF000, pDM_PSTable->RegA74);

			phy_set_bb_reg(adapter, 0x818, BIT28, 0x0);

			phy_set_bb_reg(adapter, 0x818, BIT(28), 0x0);

		}

		pDM_PSTable->PreRFState = pDM_PSTable->CurRFState;

	}
@@ -1229,7 +1229,7 @@ void odm_TXPowerTrackingCheckCE(struct odm_dm_struct *pDM_Odm) 
		return;



	if (!pDM_Odm->RFCalibrateInfo.TM_Trigger) {		/* at least delay 1 sec */

		phy_set_rf_reg(Adapter, RF_PATH_A, RF_T_METER_88E, BIT17 | BIT16, 0x03);

		phy_set_rf_reg(Adapter, RF_PATH_A, RF_T_METER_88E, BIT(17) | BIT(16), 0x03);



		pDM_Odm->RFCalibrateInfo.TM_Trigger = 1;

		return;

drivers/staging/rtl8188eu/hal/odm_HWConfig.c

+2 −2
Original line number Diff line number Diff line
@@ -362,7 +362,7 @@ static void odm_Process_RSSIForDM(struct odm_dm_struct *dm_odm, 
				}

			}



			pEntry->rssi_stat.PacketMap = (pEntry->rssi_stat.PacketMap<<1) | BIT0;

			pEntry->rssi_stat.PacketMap = (pEntry->rssi_stat.PacketMap<<1) | BIT(0);



		} else {

			RSSI_Ave = pPhyInfo->RxPWDBAll;
@@ -391,7 +391,7 @@ static void odm_Process_RSSIForDM(struct odm_dm_struct *dm_odm, 
			pEntry->rssi_stat.ValidBit++;



		for (i = 0; i < pEntry->rssi_stat.ValidBit; i++)

			OFDM_pkt += (u8)(pEntry->rssi_stat.PacketMap>>i)&BIT0;

			OFDM_pkt += (u8)(pEntry->rssi_stat.PacketMap>>i) & BIT(0);



		if (pEntry->rssi_stat.ValidBit == 64) {

			Weighting = ((OFDM_pkt<<4) > 64) ? 64 : (OFDM_pkt<<4);

drivers/staging/rtl8188eu/hal/odm_RTL8188E.c

+58 −58
Original line number Diff line number Diff line
@@ -28,26 +28,26 @@ static void dm_rx_hw_antena_div_init(struct odm_dm_struct *dm_odm) 


	if (*(dm_odm->mp_mode) == 1) {

		dm_odm->AntDivType = CGCS_RX_SW_ANTDIV;

		phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT7, 0);

		phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT31, 1);

		phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT(7), 0);

		phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(31), 1);

		return;

	}



	/* MAC Setting */

	value32 = phy_query_bb_reg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord);

	phy_set_bb_reg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord,

		       value32|(BIT23|BIT25));

		       value32|(BIT(23) | BIT(25)));

	/* Pin Settings */

	phy_set_bb_reg(adapter, ODM_REG_PIN_CTRL_11N, BIT9|BIT8, 0);

	phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT10, 0);

	phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT22, 1);

	phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT31, 1);

	phy_set_bb_reg(adapter, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);

	phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0);

	phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(22), 1);

	phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(31), 1);

	/* OFDM Settings */

	phy_set_bb_reg(adapter, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord,

		       0x000000a0);

	/* CCK Settings */

	phy_set_bb_reg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT7, 1);

	phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT4, 1);

	phy_set_bb_reg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1);

	phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1);

	rtl88eu_dm_update_rx_idle_ant(dm_odm, MAIN_ANT);

	phy_set_bb_reg(adapter, ODM_REG_ANT_MAPPING1_11N, 0xFFFF, 0x0201);

}
@@ -59,37 +59,37 @@ static void dm_trx_hw_antenna_div_init(struct odm_dm_struct *dm_odm) 


	if (*(dm_odm->mp_mode) == 1) {

		dm_odm->AntDivType = CGCS_RX_SW_ANTDIV;

		phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT7, 0);

		phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT(7), 0);

		phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N,

			       BIT5|BIT4|BIT3, 0);

			       BIT(5) | BIT(4) | BIT(3), 0);

		return;

	}



	/* MAC Setting */

	value32 = phy_query_bb_reg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord);

	phy_set_bb_reg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord,

		       value32|(BIT23|BIT25));

		       value32|(BIT(23) | BIT(25)));

	/* Pin Settings */

	phy_set_bb_reg(adapter, ODM_REG_PIN_CTRL_11N, BIT9|BIT8, 0);

	phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT10, 0);

	phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT22, 0);

	phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT31, 1);

	phy_set_bb_reg(adapter, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);

	phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0);

	phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(22), 0);

	phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(31), 1);

	/* OFDM Settings */

	phy_set_bb_reg(adapter, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord,

		       0x000000a0);

	/* CCK Settings */

	phy_set_bb_reg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT7, 1);

	phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT4, 1);

	phy_set_bb_reg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1);

	phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1);

	/* Tx Settings */

	phy_set_bb_reg(adapter, ODM_REG_TX_ANT_CTRL_11N, BIT21, 0);

	phy_set_bb_reg(adapter, ODM_REG_TX_ANT_CTRL_11N, BIT(21), 0);

	rtl88eu_dm_update_rx_idle_ant(dm_odm, MAIN_ANT);



	/* antenna mapping table */

	if (!dm_odm->bIsMPChip) { /* testchip */

		phy_set_bb_reg(adapter, ODM_REG_RX_DEFUALT_A_11N,

			       BIT10|BIT9|BIT8, 1);

			       BIT(10) | BIT(9) | BIT(8), 1);

		phy_set_bb_reg(adapter, ODM_REG_RX_DEFUALT_A_11N,

			       BIT13|BIT12|BIT11, 2);

			       BIT(13) | BIT(12) | BIT(11), 2);

	} else { /* MPchip */

		phy_set_bb_reg(adapter, ODM_REG_ANT_MAPPING1_11N, bMaskDWord,

			       0x0201);
@@ -118,40 +118,40 @@ static void dm_fast_training_init(struct odm_dm_struct *dm_odm) 


	/* MAC Setting */

	value32 = phy_query_bb_reg(adapter, 0x4c, bMaskDWord);

	phy_set_bb_reg(adapter, 0x4c, bMaskDWord, value32|(BIT23|BIT25));

	phy_set_bb_reg(adapter, 0x4c, bMaskDWord, value32|(BIT(23) | BIT(25)));

	value32 = phy_query_bb_reg(adapter,  0x7B4, bMaskDWord);

	phy_set_bb_reg(adapter, 0x7b4, bMaskDWord, value32|(BIT16|BIT17));

	phy_set_bb_reg(adapter, 0x7b4, bMaskDWord, value32|(BIT(16) | BIT(17)));



	/* Match MAC ADDR */

	phy_set_bb_reg(adapter, 0x7b4, 0xFFFF, 0);

	phy_set_bb_reg(adapter, 0x7b0, bMaskDWord, 0);



	phy_set_bb_reg(adapter, 0x870, BIT9|BIT8, 0);

	phy_set_bb_reg(adapter, 0x864, BIT10, 0);

	phy_set_bb_reg(adapter, 0xb2c, BIT22, 0);

	phy_set_bb_reg(adapter, 0xb2c, BIT31, 1);

	phy_set_bb_reg(adapter, 0x870, BIT(9) | BIT(8), 0);

	phy_set_bb_reg(adapter, 0x864, BIT(10), 0);

	phy_set_bb_reg(adapter, 0xb2c, BIT(22), 0);

	phy_set_bb_reg(adapter, 0xb2c, BIT(31), 1);

	phy_set_bb_reg(adapter, 0xca4, bMaskDWord, 0x000000a0);



	/* antenna mapping table */

	if (AntCombination == 2) {

		if (!dm_odm->bIsMPChip) { /* testchip */

			phy_set_bb_reg(adapter, 0x858, BIT10|BIT9|BIT8, 1);

			phy_set_bb_reg(adapter, 0x858, BIT13|BIT12|BIT11, 2);

			phy_set_bb_reg(adapter, 0x858, BIT(10) | BIT(9) | BIT(8), 1);

			phy_set_bb_reg(adapter, 0x858, BIT(13) | BIT(12) | BIT(11), 2);

		} else { /* MPchip */

			phy_set_bb_reg(adapter, 0x914, bMaskByte0, 1);

			phy_set_bb_reg(adapter, 0x914, bMaskByte1, 2);

		}

	} else if (AntCombination == 7) {

		if (!dm_odm->bIsMPChip) { /* testchip */

			phy_set_bb_reg(adapter, 0x858, BIT10|BIT9|BIT8, 0);

			phy_set_bb_reg(adapter, 0x858, BIT13|BIT12|BIT11, 1);

			phy_set_bb_reg(adapter, 0x878, BIT16, 0);

			phy_set_bb_reg(adapter, 0x858, BIT15|BIT14, 2);

			phy_set_bb_reg(adapter, 0x878, BIT19|BIT18|BIT17, 3);

			phy_set_bb_reg(adapter, 0x878, BIT22|BIT21|BIT20, 4);

			phy_set_bb_reg(adapter, 0x878, BIT25|BIT24|BIT23, 5);

			phy_set_bb_reg(adapter, 0x878, BIT28|BIT27|BIT26, 6);

			phy_set_bb_reg(adapter, 0x878, BIT31|BIT30|BIT29, 7);

			phy_set_bb_reg(adapter, 0x858, BIT(10) | BIT(9) | BIT(8), 0);

			phy_set_bb_reg(adapter, 0x858, BIT(13) | BIT(12) | BIT(11), 1);

			phy_set_bb_reg(adapter, 0x878, BIT(16), 0);

			phy_set_bb_reg(adapter, 0x858, BIT(15) | BIT(14), 2);

			phy_set_bb_reg(adapter, 0x878, BIT(19) | BIT(18) | BIT(17), 3);

			phy_set_bb_reg(adapter, 0x878, BIT(22) | BIT(21) | BIT(20), 4);

			phy_set_bb_reg(adapter, 0x878, BIT(25) | BIT(24) | BIT(23), 5);

			phy_set_bb_reg(adapter, 0x878, BIT(28) | BIT(27) | BIT(26), 6);

			phy_set_bb_reg(adapter, 0x878, BIT(31) | BIT(30) | BIT(29), 7);

		} else { /* MPchip */

			phy_set_bb_reg(adapter, 0x914, bMaskByte0, 0);

			phy_set_bb_reg(adapter, 0x914, bMaskByte1, 1);
@@ -165,13 +165,13 @@ static void dm_fast_training_init(struct odm_dm_struct *dm_odm) 
	}



	/* Default Ant Setting when no fast training */

	phy_set_bb_reg(adapter, 0x80c, BIT21, 1);

	phy_set_bb_reg(adapter, 0x864, BIT5|BIT4|BIT3, 0);

	phy_set_bb_reg(adapter, 0x864, BIT8|BIT7|BIT6, 1);

	phy_set_bb_reg(adapter, 0x80c, BIT(21), 1);

	phy_set_bb_reg(adapter, 0x864, BIT(5) | BIT(4) | BIT(3), 0);

	phy_set_bb_reg(adapter, 0x864, BIT(8) | BIT(7) | BIT(6), 1);



	/* Enter Traing state */

	phy_set_bb_reg(adapter, 0x864, BIT2|BIT1|BIT0, (AntCombination-1));

	phy_set_bb_reg(adapter, 0xc50, BIT7, 1);

	phy_set_bb_reg(adapter, 0x864, BIT(2) | BIT(1) | BIT(0), (AntCombination-1));

	phy_set_bb_reg(adapter, 0xc50, BIT(7), 1);

}



void rtl88eu_dm_antenna_div_init(struct odm_dm_struct *dm_odm)
@@ -205,18 +205,18 @@ void rtl88eu_dm_update_rx_idle_ant(struct odm_dm_struct *dm_odm, u8 ant) 


		if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) {

			phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N,

				       BIT5|BIT4|BIT3, default_ant);

				       BIT(5) | BIT(4) | BIT(3), default_ant);

			phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N,

				       BIT8|BIT7|BIT6, optional_ant);

				       BIT(8) | BIT(7) | BIT(6), optional_ant);

			phy_set_bb_reg(adapter, ODM_REG_ANTSEL_CTRL_11N,

				       BIT14|BIT13|BIT12, default_ant);

				       BIT(14) | BIT(13) | BIT(12), default_ant);

			phy_set_bb_reg(adapter, ODM_REG_RESP_TX_11N,

				       BIT6|BIT7, default_ant);

				       BIT(6) | BIT(7), default_ant);

		} else if (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV) {

			phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N,

				       BIT5|BIT4|BIT3, default_ant);

				       BIT(5) | BIT(4) | BIT(3), default_ant);

			phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N,

				       BIT8|BIT7|BIT6, optional_ant);

				       BIT(8) | BIT(7) | BIT(6), optional_ant);

		}

	}

	dm_fat_tbl->RxIdleAnt = ant;
@@ -231,9 +231,9 @@ static void update_tx_ant_88eu(struct odm_dm_struct *dm_odm, u8 ant, u32 mac_id) 
		target_ant = MAIN_ANT_CG_TRX;

	else

		target_ant = AUX_ANT_CG_TRX;

	dm_fat_tbl->antsel_a[mac_id] = target_ant&BIT0;

	dm_fat_tbl->antsel_b[mac_id] = (target_ant&BIT1)>>1;

	dm_fat_tbl->antsel_c[mac_id] = (target_ant&BIT2)>>2;

	dm_fat_tbl->antsel_a[mac_id] = target_ant & BIT(0);

	dm_fat_tbl->antsel_b[mac_id] = (target_ant & BIT(1))>>1;

	dm_fat_tbl->antsel_c[mac_id] = (target_ant & BIT(2))>>2;

}



void rtl88eu_dm_set_tx_ant_by_tx_info(struct odm_dm_struct *dm_odm,
@@ -344,12 +344,12 @@ void rtl88eu_dm_antenna_diversity(struct odm_dm_struct *dm_odm) 
		if (dm_fat_tbl->bBecomeLinked) {

			ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,

				     ("Need to Turn off HW AntDiv\n"));

			phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT7, 0);

			phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT(7), 0);

			phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA1_11N,

				       BIT15, 0);

				       BIT(15), 0);

			if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV)

				phy_set_bb_reg(adapter, ODM_REG_TX_ANT_CTRL_11N,

					       BIT21, 0);

					       BIT(21), 0);

			dm_fat_tbl->bBecomeLinked = dm_odm->bLinked;

		}

		return;
@@ -357,12 +357,12 @@ void rtl88eu_dm_antenna_diversity(struct odm_dm_struct *dm_odm) 
		if (!dm_fat_tbl->bBecomeLinked) {

			ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,

				     ("Need to Turn on HW AntDiv\n"));

			phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT7, 1);

			phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT(7), 1);

			phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA1_11N,

				       BIT15, 1);

				       BIT(15), 1);

			if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV)

				phy_set_bb_reg(adapter, ODM_REG_TX_ANT_CTRL_11N,

					       BIT21, 1);

					       BIT(21), 1);

			dm_fat_tbl->bBecomeLinked = dm_odm->bLinked;

		}

	}