Merge "ARM: dts: msm: Add GDSC, GCC and CPU nodes for MSM8937"

                        "qcom,gcc-gfx-8953"

                        "qcom,gcc-gfx-sdm450"

                        "qcom,gcc-gfx-sdm632"

			"qcom,gcc-8992"

			"qcom,gcc-8952"

			"qcom,gcc-8937"

			"qcom,gcc-8917"

			"qcom,gcc-8940"

			"qcom,gcc-8920"

			"qcom,gcc-spm-8952"

			"qcom,gcc-spm-8937"

			"qcom,cc-debug-8952"

			"qcom,cc-debug-8953"

			"qcom,cc-debug-8937"

			"qcom,cc-debug-8917"

			"qcom,cc-debug-8940"

			"qcom,cc-debug-8920"

			"qcom,gcc-mdss-8953"

			"qcom,gcc-mdss-8952"

			"qcom,gcc-mdss-8937"

			"qcom,gcc-mdss-8917"

			"qcom,gcc-mdss-8940"

			"qcom,gcc-mdss-8920"

			"qcom,gcc-gfx-8953"

			"qcom,gcc-gfx-sdm450"

- reg:                  Pairs of physical base addresses and region sizes of

                        memory mapped registers.

Qualcomm Technology MSM8939 CPU clock tree

clock-cpu-8939 is a device that represents the MSM8939 or MSM8952 CPU

subsystem clock tree. It lists the various power supplies that need to be

scaled when the clocks are scaled and also other HW specific parameters like

fmax tables, avs settings table, etc.

Required properties:

- compatible:		Must be one of "qcom,clock-cpu-8939" or

			"qcom,cpu-clock-8952", "qcom,cpu-clock-8917".

- reg:			Pairs of physical base addresses and region sizes of

			memory mapped registers.

- reg-names:		Names of the bases for the above registers. Expected

			bases are:

			"apcs-c0-rcg-base", "apcs-c1-rcg-base",

			"apcs-cci-rcg-base", "efuse", "efuse1", "efuse2"

- vdd-c0-supply:	The regulator powering the little cluster

- vdd-c1-supply:	The regulator powering the big cluster

- vdd-cci-supply:	The regulator powering the CCI cluster

- qcom,speedX-bin-vY-ZZZ:

			A table of CPU frequency (Hz) to voltage (corner)

			mapping that represents the max frequency possible

			for each supported voltage level for a CPU. 'X' is

			the speed bin into which the device falls into - a

			bin will have unique frequency-voltage relationships.

			'Y' is the characterization version, implying that

			characterization (deciding what speed bin a device

			falls into) methods and/or encoding may change. The

			values 'X' and 'Y' are read from efuse registers, and

			the right table is picked from multiple possible tables.

			'ZZZ' can be c1, c0 or cci depending on whether the table

			is for the big cluster, little cluster or cci.

Optional properties:

- qcom,cpu-pcnoc-vote:  Boolean to indicate cpu clocks would need to keep

			active pcnoc vote.

- qcom,num-cluster:     Boolean to indicate cpu clock code is used for single

			cluster.

Example:

	clock_cpu: qcom,cpu-clock-8939@f9015000 {

		compatible = "qcom,cpu-clock-8939";

		reg = <0xf9015000 0x1000>,

		      <0xf9016000 0x1000>,

		      <0xf9011000 0x1000>,

		      <0xf900d000 0x1000>,

		      <0xf900f000 0x1000>,

		      <0xf9112000 0x1000>;

		reg-names = "apcs-c0-rcg-base", "apcs-c1-rcg-base",

			     "apcs-cci-rcg-base", "efuse", "efuse1",

				"efuse2";

                vdd-c0-supply = <&apc_vreg_corner>;

		vdd-c1-supply = <&apc_vreg_corner>;

		vdd-cci-supply = <&apc_vreg_corner>;

		qcom,speed0-bin-v0-c0 =

			<         0 0>,

			< 384000000 1>,

			< 787200000 2>,

			<1286400000 3>;

		qcom,speed0-bin-v0-c1 =

			<         0 0>,

			< 384000000 1>,

			< 787200000 2>,

			<1785600000 3>;

		qcom,speed0-bin-v0-cci =

			<         0 0>,

			< 150000000 1>,

			< 300000000 2>,

			< 600000000 3>;

		clocks = <&clock_gcc clk_gpll0_ao>,

			<&clock_gcc clk_a53ss_c0_pll>,

			<&clock_gcc clk_gpll0_ao>,

			<&clock_gcc clk_a53ss_c1_pll>,

			<&clock_gcc clk_gpll0_ao>,

			<&clock_gcc clk_a53ss_cci_pll>;

			clock-names = "clk-c0-4", "clk-c0-5",

			"clk-c1-4", "clk-c1-5",

			"clk-cci-4", "clk-cci-5";

		#clock-cells = <1>;

};

#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>

#include <dt-bindings/spmi/spmi.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/clock/msm-clocks-8952.h>

/ {

	model = "Qualcomm Technologies, Inc. MSM8937";

		qcom,summing-threshold = <10>;

	};

	clock_gcc: qcom,gcc@1800000 {

		#address-cells = <1>;

		#size-cells = <1>;

		compatible = "qcom,gcc-8937";

		reg = <0x1800000 0x80000>,

			<0xb016000 0x00040>,

			<0xb116000 0x00040>,

			<0x00a6018 0x00004>;

		reg-names = "cc_base", "apcs_c1_base",

				"apcs_c0_base", "efuse";

		vdd_dig-supply = <&pm8937_s2_level>;

		vdd_sr2_dig-supply = <&pm8937_s2_level_ao>;

		vdd_sr2_pll-supply = <&pm8937_l7_ao>;

		vdd_hf_dig-supply = <&pm8937_s2_level_ao>;

		vdd_hf_pll-supply = <&pm8937_l7_ao>;

		#clock-cells = <1>;

		#reset-cells = <1>;

		ranges;

		qcom,spm@0 {

			compatible = "qcom,gcc-spm-8937";

			reg = <0x0b111200 0x100>,

				<0x0b011200 0x100>;

			reg-names = "spm_c0_base", "spm_c1_base";

		};

	};

	clock_debug: qcom,cc-debug@1874000 {

		compatible = "qcom,cc-debug-8937";

		reg = <0x1874000 0x4>,

			<0xb11101c 0x8>;

		reg-names = "cc_base", "meas";

		#clock-cells = <1>;

	};

	clock_cpu: qcom,cpu-clock-8939@b111050 {

		compatible = "qcom,cpu-clock-8939";

		reg =   <0xb011050 0x8>,

			<0xb111050 0x8>,

			<0xb1d1050 0x8>,

			<0x00a412c 0x8>;

		reg-names = "apcs-c1-rcg-base", "apcs-c0-rcg-base",

				"apcs-cci-rcg-base", "efuse";

		vdd-c0-supply = <&apc_vreg_corner>;

		vdd-c1-supply = <&apc_vreg_corner>;

		vdd-cci-supply = <&apc_vreg_corner>;

		clocks = <&clock_gcc clk_gpll0_ao_clk_src>,

			<&clock_gcc clk_a53ss_c0_pll>,

			<&clock_gcc clk_gpll0_ao_clk_src>,

			<&clock_gcc clk_a53ss_c1_pll>,

			<&clock_gcc clk_gpll0_ao_clk_src>,

			<&clock_gcc clk_gpll0_ao_clk_src>;

		clock-names = "clk-c0-4", "clk-c0-5",

				"clk-c1-4", "clk-c1-5",

				"clk-cci-4", "clk-cci-2";

		qcom,speed0-bin-v0-c0 =

			<          0 0>,

			<  768000000 1>,

			<  902400000 2>,

			<  998400000 4>,

			< 1094400000 6>;

		qcom,speed0-bin-v0-c1 =

			<          0 0>,

			<  960000000 1>,

			< 1094400000 2>,

			< 1248000000 4>,

			< 1344000000 5>,

			< 1401000000 6>;

		qcom,speed0-bin-v0-cci =

			<          0 0>,

			<  400000000 1>,

			<  533333333 3>;

		qcom,speed1-bin-v0-c0 =

			<          0 0>,

			<  768000000 1>,

			<  902400000 2>,

			<  998400000 4>,

			< 1094400000 6>,

			< 1209600000 7>;

		qcom,speed1-bin-v0-c1 =

			<          0 0>,

			<  960000000 1>,

			< 1094400000 2>,

			< 1248000000 4>,

			< 1344000000 5>,

			< 1401000000 6>,

			< 1497600000 7>;

		qcom,speed1-bin-v0-cci =

			<          0 0>,

			<  400000000 1>,

			<  533333333 3>;

		qcom,speed2-bin-v0-c0 =

			<          0 0>,

			<  768000000 1>,

			<  902400000 2>,

			<  998400000 3>;

		qcom,speed2-bin-v0-c1 =

			<          0 0>,

			<  960000000 1>,

			< 1094400000 2>,

			< 1209600000 3>;

		qcom,speed2-bin-v0-cci =

			<          0 0>,

			<  400000000 1>,

			<  533333333 3>;

		#clock-cells = <1>;

	};

	cpubw: qcom,cpubw {

		compatible = "qcom,devbw";

#include "pm8937-rpm-regulator.dtsi"

#include "msm8937-regulator.dtsi"

#include "pm8937.dtsi"

#include "msm-gdsc-8916.dtsi"

&gdsc_venus {

	clock-names = "bus_clk", "core_clk";

	clocks = <&clock_gcc clk_gcc_venus0_axi_clk>,

		<&clock_gcc clk_gcc_venus0_vcodec0_clk>;

	status = "okay";

};

&gdsc_venus_core0 {

	qcom,support-hw-trigger;

	clock-names ="core0_clk";

	clocks = <&clock_gcc clk_gcc_venus0_core0_vcodec0_clk>;

	status = "okay";

};

&gdsc_mdss {

	clock-names = "core_clk", "bus_clk";

	clocks = <&clock_gcc clk_gcc_mdss_mdp_clk>,

		<&clock_gcc clk_gcc_mdss_axi_clk>;

	qcom,disallow-clear;

	status = "okay";

};

&gdsc_jpeg {

	clock-names = "core_clk", "bus_clk";

	clocks = <&clock_gcc clk_gcc_camss_jpeg0_clk>,

		<&clock_gcc clk_gcc_camss_jpeg_axi_clk>;

	status = "okay";

};

&gdsc_vfe {

	clock-names = "core_clk", "bus_clk", "micro_clk",

			"csi_clk";

	clocks = <&clock_gcc clk_gcc_camss_vfe0_clk>,

		<&clock_gcc clk_gcc_camss_vfe_axi_clk>,

		<&clock_gcc clk_gcc_camss_micro_ahb_clk>,

		<&clock_gcc clk_gcc_camss_csi_vfe0_clk>;

	status = "okay";

};

&gdsc_vfe1 {

	clock-names = "core_clk", "bus_clk", "micro_clk",

			"csi_clk";

	clocks = <&clock_gcc clk_gcc_camss_vfe1_clk>,

		<&clock_gcc clk_gcc_camss_vfe1_axi_clk>,

		<&clock_gcc clk_gcc_camss_micro_ahb_clk>,

		<&clock_gcc clk_gcc_camss_csi_vfe1_clk>;

	status = "okay";

};

&gdsc_cpp {

	clock-names = "core_clk", "bus_clk";

	clocks = <&clock_gcc clk_gcc_camss_cpp_clk>,

		<&clock_gcc clk_gcc_camss_cpp_axi_clk>;

	status = "okay";

};

&gdsc_oxili_gx {

	clock-names = "core_root_clk";

	clocks =<&clock_gcc clk_gfx3d_clk_src>;

	qcom,enable-root-clk;

	qcom,clk-dis-wait-val = <0x5>;

	status = "okay";

};

&gdsc_oxili_cx {

	reg = <0x1859044 0x4>;

	clock-names = "core_clk";

	clocks = <&clock_gcc clk_gcc_oxili_gfx3d_clk>;

	status = "okay";

};

obj-$(CONFIG_ARCH_MSM8953)	+= clock-gcc-8953.o

obj-$(CONFIG_ARCH_MSM8953)	+= clock-cpu-8953.o

obj-$(CONFIG_ARCH_MSM8953)	+= clock-rcgwr.o

obj-$(CONFIG_ARCH_MSM8937)	+= clock-gcc-8952.o

obj-$(CONFIG_ARCH_MSM8937)	+= clock-cpu-8939.o

obj-$(CONFIG_ARCH_MSM8937)	+= clock-rcgwr.o

endif

obj-y               += mdss/