Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 9b229d8b authored by Rahul Sharma's avatar Rahul Sharma Committed by Mike Turquette
Browse files

clk/exynos5420: add gate clock for mixer sysmmu 



Adding sysmmu clock for mixer for exynos5420.

Signed-off-by: default avatarRahul Sharma <rahul.sharma@samsung.com>
Acked-by: default avatarTomasz Figa <t.figa@samsung.com>
Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
parent c9f3f081

Documentation/devicetree/bindings/clock/exynos5420-clock.txt

+1 −0
Original line number Diff line number Diff line
@@ -180,6 +180,7 @@ clock which they consume. 
  fimc_lite3		495

  aclk_g3d		500

  g3d			501

  smmu_mixer		502



Example 1: An example of a clock controller node is listed below.

drivers/clk/samsung/clk-exynos5420.c

+2 −1
Original line number Diff line number Diff line
@@ -138,7 +138,7 @@ enum exynos5420_clks { 
	aclk300_gscl = 460, smmu_gscl0, smmu_gscl1, gscl_wa, gscl_wb, gscl0,

	gscl1, clk_3aa, aclk266_g2d = 470, sss, slim_sss, mdma0,

	aclk333_g2d = 480, g2d, aclk333_432_gscl = 490, smmu_3aa, smmu_fimcl0,

	smmu_fimcl1, smmu_fimcl3, fimc_lite3, aclk_g3d = 500, g3d,

	smmu_fimcl1, smmu_fimcl3, fimc_lite3, aclk_g3d = 500, g3d, smmu_mixer,



	nr_clks,

};
@@ -725,6 +725,7 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { 
	GATE(smmu_mscl0, "smmu_mscl0", "aclk400_mscl", GATE_IP_MSCL, 8, 0, 0),

	GATE(smmu_mscl1, "smmu_mscl1", "aclk400_mscl", GATE_IP_MSCL, 9, 0, 0),

	GATE(smmu_mscl2, "smmu_mscl2", "aclk400_mscl", GATE_IP_MSCL, 10, 0, 0),

	GATE(smmu_mixer, "smmu_mixer", "aclk200_disp1", GATE_IP_DISP1, 9, 0, 0),

};



static struct samsung_pll_clock exynos5420_plls[nr_plls] __initdata = {