Loading drivers/power/supply/qcom/fg-memif.c +6 −0 Original line number Diff line number Diff line Loading @@ -777,6 +777,12 @@ static int fg_direct_mem_request(struct fg_chip *chip, bool request) if (!request) return 0; /* * HW takes 5 cycles (200 KHz clock) to grant access after requesting * for DMA. Wait for 40 us before polling for MEM_GNT first time. */ usleep_range(40, 41); while (i < MEM_GNT_RETRIES) { rc = fg_read(chip, MEM_IF_INT_RT_STS(chip), &val, 1); if (rc < 0) { Loading drivers/power/supply/qcom/qpnp-fg-gen3.c +6 −2 Original line number Diff line number Diff line Loading @@ -2093,8 +2093,12 @@ static int fg_adjust_recharge_soc(struct fg_chip *chip) return 0; } } else { /* Charging, do nothing */ if (!chip->recharge_soc_adjusted) return 0; /* Restore the default value */ new_recharge_soc = recharge_soc; chip->recharge_soc_adjusted = false; } } else { /* Restore the default value */ Loading Loading
drivers/power/supply/qcom/fg-memif.c +6 −0 Original line number Diff line number Diff line Loading @@ -777,6 +777,12 @@ static int fg_direct_mem_request(struct fg_chip *chip, bool request) if (!request) return 0; /* * HW takes 5 cycles (200 KHz clock) to grant access after requesting * for DMA. Wait for 40 us before polling for MEM_GNT first time. */ usleep_range(40, 41); while (i < MEM_GNT_RETRIES) { rc = fg_read(chip, MEM_IF_INT_RT_STS(chip), &val, 1); if (rc < 0) { Loading
drivers/power/supply/qcom/qpnp-fg-gen3.c +6 −2 Original line number Diff line number Diff line Loading @@ -2093,8 +2093,12 @@ static int fg_adjust_recharge_soc(struct fg_chip *chip) return 0; } } else { /* Charging, do nothing */ if (!chip->recharge_soc_adjusted) return 0; /* Restore the default value */ new_recharge_soc = recharge_soc; chip->recharge_soc_adjusted = false; } } else { /* Restore the default value */ Loading