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Commit 9a97af7e authored by Kalle Valo's avatar Kalle Valo
Browse files

Merge remote branch 'wireless-next/master' into ath6kl-next

parents 59500b48 e3bea1c8

drivers/net/wireless/ath/ath9k/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ config ATH9K 


config ATH9K_PCI

	bool "Atheros ath9k PCI/PCIe bus support"

	default y

	depends on ATH9K && PCI

	---help---

	  This option enables the PCI bus support in ath9k.

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

+75 −65
Original line number Diff line number Diff line
@@ -121,10 +121,8 @@ static const struct ar9300_eeprom ar9300_default = { 
		 * if the register is per chain

		 */

		.noiseFloorThreshCh = {-1, 0, 0},

		.ob = {1, 1, 1},/* 3 chain */

		.db_stage2 = {1, 1, 1}, /* 3 chain  */

		.db_stage3 = {0, 0, 0},

		.db_stage4 = {0, 0, 0},

		.reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},

		.quick_drop = 0,

		.xpaBiasLvl = 0,

		.txFrameToDataStart = 0x0e,

		.txFrameToPaOn = 0x0e,
@@ -144,7 +142,7 @@ static const struct ar9300_eeprom ar9300_default = { 
	 },

	.base_ext1 = {

		.ant_div_control = 0,

		.future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}

		.future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}

	},

	.calFreqPier2G = {

		FREQ2FBIN(2412, 1),
@@ -323,10 +321,8 @@ static const struct ar9300_eeprom ar9300_default = { 
		.spurChans = {0, 0, 0, 0, 0},

		/* noiseFloorThreshCh Check if the register is per chain */

		.noiseFloorThreshCh = {-1, 0, 0},

		.ob = {3, 3, 3}, /* 3 chain */

		.db_stage2 = {3, 3, 3}, /* 3 chain */

		.db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */

		.db_stage4 = {3, 3, 3},	 /* don't exist for 2G */

		.reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},

		.quick_drop = 0,

		.xpaBiasLvl = 0,

		.txFrameToDataStart = 0x0e,

		.txFrameToPaOn = 0x0e,
@@ -698,10 +694,8 @@ static const struct ar9300_eeprom ar9300_x113 = { 
		 * if the register is per chain

		 */

		.noiseFloorThreshCh = {-1, 0, 0},

		.ob = {1, 1, 1},/* 3 chain */

		.db_stage2 = {1, 1, 1}, /* 3 chain  */

		.db_stage3 = {0, 0, 0},

		.db_stage4 = {0, 0, 0},

		.reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},

		.quick_drop = 0,

		.xpaBiasLvl = 0,

		.txFrameToDataStart = 0x0e,

		.txFrameToPaOn = 0x0e,
@@ -721,7 +715,7 @@ static const struct ar9300_eeprom ar9300_x113 = { 
	 },

	 .base_ext1 = {

		.ant_div_control = 0,

		.future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}

		.future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}

	 },

	.calFreqPier2G = {

		FREQ2FBIN(2412, 1),
@@ -900,10 +894,8 @@ static const struct ar9300_eeprom ar9300_x113 = { 
		.spurChans = {FREQ2FBIN(5500, 0), 0, 0, 0, 0},

		/* noiseFloorThreshCh Check if the register is per chain */

		.noiseFloorThreshCh = {-1, 0, 0},

		.ob = {3, 3, 3}, /* 3 chain */

		.db_stage2 = {3, 3, 3}, /* 3 chain */

		.db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */

		.db_stage4 = {3, 3, 3},	 /* don't exist for 2G */

		.reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},

		.quick_drop = 0,

		.xpaBiasLvl = 0xf,

		.txFrameToDataStart = 0x0e,

		.txFrameToPaOn = 0x0e,
@@ -1276,10 +1268,8 @@ static const struct ar9300_eeprom ar9300_h112 = { 
		 * if the register is per chain

		 */

		.noiseFloorThreshCh = {-1, 0, 0},

		.ob = {1, 1, 1},/* 3 chain */

		.db_stage2 = {1, 1, 1}, /* 3 chain  */

		.db_stage3 = {0, 0, 0},

		.db_stage4 = {0, 0, 0},

		.reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},

		.quick_drop = 0,

		.xpaBiasLvl = 0,

		.txFrameToDataStart = 0x0e,

		.txFrameToPaOn = 0x0e,
@@ -1291,20 +1281,20 @@ static const struct ar9300_eeprom ar9300_h112 = { 
		.txEndToRxOn = 0x2,

		.txFrameToXpaOn = 0xe,

		.thresh62 = 28,

		.papdRateMaskHt20 = LE32(0x80c080),

		.papdRateMaskHt40 = LE32(0x80c080),

		.papdRateMaskHt20 = LE32(0x0c80c080),

		.papdRateMaskHt40 = LE32(0x0080c080),

		.futureModal = {

			0, 0, 0, 0, 0, 0, 0, 0,

		},

	},

	.base_ext1 = {

		.ant_div_control = 0,

		.future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}

		.future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}

	},

	.calFreqPier2G = {

		FREQ2FBIN(2412, 1),

		FREQ2FBIN(2437, 1),

		FREQ2FBIN(2472, 1),

		FREQ2FBIN(2462, 1),

	},

	/* ar9300_cal_data_per_freq_op_loop 2g */

	.calPierData2G = {
@@ -1314,7 +1304,7 @@ static const struct ar9300_eeprom ar9300_h112 = { 
	},

	.calTarget_freqbin_Cck = {

		FREQ2FBIN(2412, 1),

		FREQ2FBIN(2484, 1),

		FREQ2FBIN(2472, 1),

	},

	.calTarget_freqbin_2G = {

		FREQ2FBIN(2412, 1),
@@ -1478,10 +1468,8 @@ static const struct ar9300_eeprom ar9300_h112 = { 
		.spurChans = {0, 0, 0, 0, 0},

		/* noiseFloorThreshCh Check if the register is per chain */

		.noiseFloorThreshCh = {-1, 0, 0},

		.ob = {3, 3, 3}, /* 3 chain */

		.db_stage2 = {3, 3, 3}, /* 3 chain */

		.db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */

		.db_stage4 = {3, 3, 3},	 /* don't exist for 2G */

		.reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},

		.quick_drop = 0,

		.xpaBiasLvl = 0,

		.txFrameToDataStart = 0x0e,

		.txFrameToPaOn = 0x0e,
@@ -1515,7 +1503,7 @@ static const struct ar9300_eeprom ar9300_h112 = { 
		FREQ2FBIN(5500, 0),

		FREQ2FBIN(5600, 0),

		FREQ2FBIN(5700, 0),

		FREQ2FBIN(5825, 0)

		FREQ2FBIN(5785, 0)

	},

	.calPierData5G = {

		{
@@ -1854,10 +1842,8 @@ static const struct ar9300_eeprom ar9300_x112 = { 
		 * if the register is per chain

		 */

		.noiseFloorThreshCh = {-1, 0, 0},

		.ob = {1, 1, 1},/* 3 chain */

		.db_stage2 = {1, 1, 1}, /* 3 chain  */

		.db_stage3 = {0, 0, 0},

		.db_stage4 = {0, 0, 0},

		.reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},

		.quick_drop = 0,

		.xpaBiasLvl = 0,

		.txFrameToDataStart = 0x0e,

		.txFrameToPaOn = 0x0e,
@@ -1877,7 +1863,7 @@ static const struct ar9300_eeprom ar9300_x112 = { 
	},

	.base_ext1 = {

		.ant_div_control = 0,

		.future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}

		.future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}

	},

	.calFreqPier2G = {

		FREQ2FBIN(2412, 1),
@@ -2056,10 +2042,8 @@ static const struct ar9300_eeprom ar9300_x112 = { 
		.spurChans = {0, 0, 0, 0, 0},

		/* noiseFloorThreshch check if the register is per chain */

		.noiseFloorThreshCh = {-1, 0, 0},

		.ob = {3, 3, 3}, /* 3 chain */

		.db_stage2 = {3, 3, 3}, /* 3 chain */

		.db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */

		.db_stage4 = {3, 3, 3},	 /* don't exist for 2G */

		.reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},

		.quick_drop = 0,

		.xpaBiasLvl = 0,

		.txFrameToDataStart = 0x0e,

		.txFrameToPaOn = 0x0e,
@@ -2431,10 +2415,8 @@ static const struct ar9300_eeprom ar9300_h116 = { 
		 * if the register is per chain

		 */

		.noiseFloorThreshCh = {-1, 0, 0},

		.ob = {1, 1, 1},/* 3 chain */

		.db_stage2 = {1, 1, 1}, /* 3 chain  */

		.db_stage3 = {0, 0, 0},

		.db_stage4 = {0, 0, 0},

		.reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},

		.quick_drop = 0,

		.xpaBiasLvl = 0,

		.txFrameToDataStart = 0x0e,

		.txFrameToPaOn = 0x0e,
@@ -2454,12 +2436,12 @@ static const struct ar9300_eeprom ar9300_h116 = { 
	 },

	 .base_ext1 = {

		.ant_div_control = 0,

		.future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}

		.future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}

	 },

	.calFreqPier2G = {

		FREQ2FBIN(2412, 1),

		FREQ2FBIN(2437, 1),

		FREQ2FBIN(2472, 1),

		FREQ2FBIN(2462, 1),

	 },

	/* ar9300_cal_data_per_freq_op_loop 2g */

	.calPierData2G = {
@@ -2633,10 +2615,8 @@ static const struct ar9300_eeprom ar9300_h116 = { 
		.spurChans = {0, 0, 0, 0, 0},

		/* noiseFloorThreshCh Check if the register is per chain */

		.noiseFloorThreshCh = {-1, 0, 0},

		.ob = {3, 3, 3}, /* 3 chain */

		.db_stage2 = {3, 3, 3}, /* 3 chain */

		.db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */

		.db_stage4 = {3, 3, 3},	 /* don't exist for 2G */

		.reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},

		.quick_drop = 0,

		.xpaBiasLvl = 0,

		.txFrameToDataStart = 0x0e,

		.txFrameToPaOn = 0x0e,
@@ -2663,7 +2643,7 @@ static const struct ar9300_eeprom ar9300_h116 = { 
		.xatten1MarginHigh = {0, 0, 0}

	 },

	.calFreqPier5G = {

		FREQ2FBIN(5180, 0),

		FREQ2FBIN(5160, 0),

		FREQ2FBIN(5220, 0),

		FREQ2FBIN(5320, 0),

		FREQ2FBIN(5400, 0),
@@ -3023,6 +3003,8 @@ static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah, 
		return eep->modalHeader5G.antennaGain;

	case EEP_ANTENNA_GAIN_2G:

		return eep->modalHeader2G.antennaGain;

	case EEP_QUICK_DROP:

		return pBase->miscConfiguration & BIT(1);

	default:

		return 0;

	}
@@ -3428,25 +3410,14 @@ static u32 ar9003_dump_modal_eeprom(char *buf, u32 len, u32 size, 
	PR_EEP("Chain0 NF Threshold", modal_hdr->noiseFloorThreshCh[0]);

	PR_EEP("Chain1 NF Threshold", modal_hdr->noiseFloorThreshCh[1]);

	PR_EEP("Chain2 NF Threshold", modal_hdr->noiseFloorThreshCh[2]);

	PR_EEP("Quick Drop", modal_hdr->quick_drop);

	PR_EEP("txEndToXpaOff", modal_hdr->txEndToXpaOff);

	PR_EEP("xPA Bias Level", modal_hdr->xpaBiasLvl);

	PR_EEP("txFrameToDataStart", modal_hdr->txFrameToDataStart);

	PR_EEP("txFrameToPaOn", modal_hdr->txFrameToPaOn);

	PR_EEP("txFrameToXpaOn", modal_hdr->txFrameToXpaOn);

	PR_EEP("txClip", modal_hdr->txClip);

	PR_EEP("ADC Desired size", modal_hdr->adcDesiredSize);

	PR_EEP("Chain0 ob", modal_hdr->ob[0]);

	PR_EEP("Chain1 ob", modal_hdr->ob[1]);

	PR_EEP("Chain2 ob", modal_hdr->ob[2]);



	PR_EEP("Chain0 db_stage2", modal_hdr->db_stage2[0]);

	PR_EEP("Chain1 db_stage2", modal_hdr->db_stage2[1]);

	PR_EEP("Chain2 db_stage2", modal_hdr->db_stage2[2]);

	PR_EEP("Chain0 db_stage3", modal_hdr->db_stage3[0]);

	PR_EEP("Chain1 db_stage3", modal_hdr->db_stage3[1]);

	PR_EEP("Chain2 db_stage3", modal_hdr->db_stage3[2]);

	PR_EEP("Chain0 db_stage4", modal_hdr->db_stage4[0]);

	PR_EEP("Chain1 db_stage4", modal_hdr->db_stage4[1]);

	PR_EEP("Chain2 db_stage4", modal_hdr->db_stage4[2]);



	return len;

}
@@ -3503,6 +3474,7 @@ static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr, 
	PR_EEP("Internal regulator", !!(pBase->featureEnable & BIT(4)));

	PR_EEP("Enable Paprd", !!(pBase->featureEnable & BIT(5)));

	PR_EEP("Driver Strength", !!(pBase->miscConfiguration & BIT(0)));

	PR_EEP("Quick Drop", !!(pBase->miscConfiguration & BIT(1)));

	PR_EEP("Chain mask Reduce", (pBase->miscConfiguration >> 0x3) & 0x1);

	PR_EEP("Write enable Gpio", pBase->eepromWriteEnableGpio);

	PR_EEP("WLAN Disable Gpio", pBase->wlanDisableGpio);
@@ -3965,6 +3937,40 @@ static void ar9003_hw_apply_tuning_caps(struct ath_hw *ah) 
	}

}



static void ar9003_hw_quick_drop_apply(struct ath_hw *ah, u16 freq)

{

	struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;

	int quick_drop = ath9k_hw_ar9300_get_eeprom(ah, EEP_QUICK_DROP);

	s32 t[3], f[3] = {5180, 5500, 5785};



	if (!quick_drop)

		return;



	if (freq < 4000)

		quick_drop = eep->modalHeader2G.quick_drop;

	else {

		t[0] = eep->base_ext1.quick_drop_low;

		t[1] = eep->modalHeader5G.quick_drop;

		t[2] = eep->base_ext1.quick_drop_high;

		quick_drop = ar9003_hw_power_interpolate(freq, f, t, 3);

	}

	REG_RMW_FIELD(ah, AR_PHY_AGC, AR_PHY_AGC_QUICK_DROP, quick_drop);

}



static void ar9003_hw_txend_to_xpa_off_apply(struct ath_hw *ah, u16 freq)

{

	struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;

	u32 value;



	value = (freq < 4000) ? eep->modalHeader2G.txEndToXpaOff :

				eep->modalHeader5G.txEndToXpaOff;



	REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,

		      AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF, value);

	REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,

		      AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF, value);

}



static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,

					     struct ath9k_channel *chan)

{
@@ -3972,10 +3978,12 @@ static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah, 
	ar9003_hw_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan));

	ar9003_hw_drive_strength_apply(ah);

	ar9003_hw_atten_apply(ah, chan);

	ar9003_hw_quick_drop_apply(ah, chan->channel);

	if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah))

		ar9003_hw_internal_regulator_apply(ah);

	if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))

		ar9003_hw_apply_tuning_caps(ah);

	ar9003_hw_txend_to_xpa_off_apply(ah, chan->channel);

}



static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah,
@@ -5051,6 +5059,8 @@ static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah, 
			regulatory->max_power_level = targetPowerValT2[i];

	}



	ath9k_hw_update_regulatory_maxpower(ah);



	if (test)

		return;

drivers/net/wireless/ath/ath9k/ar9003_eeprom.h

+5 −5
Original line number Diff line number Diff line
@@ -216,10 +216,8 @@ struct ar9300_modal_eep_header { 
	u8 spurChans[AR_EEPROM_MODAL_SPURS];

	/* 3  Check if the register is per chain */

	int8_t noiseFloorThreshCh[AR9300_MAX_CHAINS];

	u8 ob[AR9300_MAX_CHAINS];

	u8 db_stage2[AR9300_MAX_CHAINS];

	u8 db_stage3[AR9300_MAX_CHAINS];

	u8 db_stage4[AR9300_MAX_CHAINS];

	u8 reserved[11];

	int8_t quick_drop;

	u8 xpaBiasLvl;

	u8 txFrameToDataStart;

	u8 txFrameToPaOn;
@@ -269,7 +267,9 @@ struct cal_ctl_data_5g { 


struct ar9300_BaseExtension_1 {

	u8 ant_div_control;

	u8 future[13];

	u8 future[11];

	int8_t quick_drop_low;

	int8_t quick_drop_high;

} __packed;



struct ar9300_BaseExtension_2 {

drivers/net/wireless/ath/ath9k/ar9003_phy.h

+2 −0
Original line number Diff line number Diff line
@@ -389,6 +389,8 @@ 
#define AR_PHY_DAG_CTRLCCK_RSSI_THR_S   10



#define AR_PHY_RIFS_INIT_DELAY         0x3ff0000

#define AR_PHY_AGC_QUICK_DROP       0x03c00000

#define AR_PHY_AGC_QUICK_DROP_S     22

#define AR_PHY_AGC_COARSE_LOW       0x00007F80

#define AR_PHY_AGC_COARSE_LOW_S     7

#define AR_PHY_AGC_COARSE_HIGH      0x003F8000

drivers/net/wireless/ath/ath9k/btcoex.c

+60 −47
Original line number Diff line number Diff line
@@ -35,6 +35,20 @@ struct ath_btcoex_config { 
	bool bt_hold_rx_clear;

};



static const u32 ar9003_wlan_weights[ATH_BTCOEX_STOMP_MAX]

				    [AR9300_NUM_WLAN_WEIGHTS] = {

	{ 0xfffffff0, 0xfffffff0, 0xfffffff0, 0xfffffff0 }, /* STOMP_ALL */

	{ 0x88888880, 0x88888880, 0x88888880, 0x88888880 }, /* STOMP_LOW */

	{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* STOMP_NONE */

};



static const u32 ar9462_wlan_weights[ATH_BTCOEX_STOMP_MAX]

				    [AR9300_NUM_WLAN_WEIGHTS] = {

	{ 0x01017d01, 0x41414101, 0x41414101, 0x41414141 }, /* STOMP_ALL */

	{ 0x01017d01, 0x3b3b3b01, 0x3b3b3b01, 0x3b3b3b3b }, /* STOMP_LOW */

	{ 0x01017d01, 0x01010101, 0x01010101, 0x01010101 }, /* STOMP_NONE */

	{ 0x01017d01, 0x013b0101, 0x3b3b0101, 0x3b3b013b }, /* STOMP_LOW_FTP */

};



void ath9k_hw_init_btcoex_hw(struct ath_hw *ah, int qnum)

{
@@ -151,27 +165,26 @@ EXPORT_SYMBOL(ath9k_hw_btcoex_set_weight); 


static void ath9k_hw_btcoex_enable_3wire(struct ath_hw *ah)

{

	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;

	struct ath_btcoex_hw *btcoex = &ah->btcoex_hw;

	u32  val;

	int i;



	/*

	 * Program coex mode and weight registers to

	 * enable coex 3-wire

	 */

	REG_WRITE(ah, AR_BT_COEX_MODE, btcoex_hw->bt_coex_mode);

	REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex_hw->bt_coex_mode2);

	REG_WRITE(ah, AR_BT_COEX_MODE, btcoex->bt_coex_mode);

	REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex->bt_coex_mode2);





	if (AR_SREV_9300_20_OR_LATER(ah)) {

		REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, ah->bt_coex_wlan_weight[0]);

		REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, ah->bt_coex_wlan_weight[1]);

		REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS0, ah->bt_coex_bt_weight[0]);

		REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS1, ah->bt_coex_bt_weight[1]);

		REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS2, ah->bt_coex_bt_weight[2]);

		REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS3, ah->bt_coex_bt_weight[3]);



		REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, btcoex->wlan_weight[0]);

		REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, btcoex->wlan_weight[1]);

		for (i = 0; i < AR9300_NUM_BT_WEIGHTS; i++)

			REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS(i),

				  btcoex->bt_weight[i]);

	} else

		REG_WRITE(ah, AR_BT_COEX_WEIGHT, btcoex_hw->bt_coex_weights);

		REG_WRITE(ah, AR_BT_COEX_WEIGHT, btcoex->bt_coex_weights);
@@ -184,10 +197,23 @@ static void ath9k_hw_btcoex_enable_3wire(struct ath_hw *ah) 
	REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);

	REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);



	ath9k_hw_cfg_output(ah, btcoex_hw->wlanactive_gpio,

	ath9k_hw_cfg_output(ah, btcoex->wlanactive_gpio,

			    AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL);

}



static void ath9k_hw_btcoex_enable_mci(struct ath_hw *ah)

{

	struct ath_btcoex_hw *btcoex = &ah->btcoex_hw;

	int i;



	for (i = 0; i < AR9300_NUM_BT_WEIGHTS; i++)

		REG_WRITE(ah, AR_MCI_COEX_WL_WEIGHTS(i),

			  btcoex->wlan_weight[i]);



	REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);

	btcoex->enabled = true;

}



void ath9k_hw_btcoex_enable(struct ath_hw *ah)

{

	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
@@ -201,6 +227,9 @@ void ath9k_hw_btcoex_enable(struct ath_hw *ah) 
	case ATH_BTCOEX_CFG_3WIRE:

		ath9k_hw_btcoex_enable_3wire(ah);

		break;

	case ATH_BTCOEX_CFG_MCI:

		ath9k_hw_btcoex_enable_mci(ah);

		return;

	}



	REG_RMW(ah, AR_GPIO_PDPU,
@@ -214,7 +243,15 @@ EXPORT_SYMBOL(ath9k_hw_btcoex_enable); 
void ath9k_hw_btcoex_disable(struct ath_hw *ah)

{

	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;



	int i;



	btcoex_hw->enabled = false;

	if (btcoex_hw->scheme == ATH_BTCOEX_CFG_MCI) {

		ath9k_hw_btcoex_bt_stomp(ah, ATH_BTCOEX_STOMP_NONE);

		for (i = 0; i < AR9300_NUM_BT_WEIGHTS; i++)

			REG_WRITE(ah, AR_MCI_COEX_WL_WEIGHTS(i),

				  btcoex_hw->wlan_weight[i]);

	}

	ath9k_hw_set_gpio(ah, btcoex_hw->wlanactive_gpio, 0);



	ath9k_hw_cfg_output(ah, btcoex_hw->wlanactive_gpio,
@@ -227,49 +264,27 @@ void ath9k_hw_btcoex_disable(struct ath_hw *ah) 
		if (AR_SREV_9300_20_OR_LATER(ah)) {

			REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, 0);

			REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, 0);

			REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS0, 0);

			REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS1, 0);

			REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS2, 0);

			REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS3, 0);

			for (i = 0; i < AR9300_NUM_BT_WEIGHTS; i++)

				REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS(i), 0);

		} else

			REG_WRITE(ah, AR_BT_COEX_WEIGHT, 0);



	}



	ah->btcoex_hw.enabled = false;

}

EXPORT_SYMBOL(ath9k_hw_btcoex_disable);



static void ar9003_btcoex_bt_stomp(struct ath_hw *ah,

			 enum ath_stomp_type stomp_type)

{

	ah->bt_coex_bt_weight[0] = AR9300_BT_WGHT;

	ah->bt_coex_bt_weight[1] = AR9300_BT_WGHT;

	ah->bt_coex_bt_weight[2] = AR9300_BT_WGHT;

	ah->bt_coex_bt_weight[3] = AR9300_BT_WGHT;





	switch (stomp_type) {

	case ATH_BTCOEX_STOMP_ALL:

		ah->bt_coex_wlan_weight[0] = AR9300_STOMP_ALL_WLAN_WGHT0;

		ah->bt_coex_wlan_weight[1] = AR9300_STOMP_ALL_WLAN_WGHT1;

		break;

	case ATH_BTCOEX_STOMP_LOW:

		ah->bt_coex_wlan_weight[0] = AR9300_STOMP_LOW_WLAN_WGHT0;

		ah->bt_coex_wlan_weight[1] = AR9300_STOMP_LOW_WLAN_WGHT1;

		break;

	case ATH_BTCOEX_STOMP_NONE:

		ah->bt_coex_wlan_weight[0] = AR9300_STOMP_NONE_WLAN_WGHT0;

		ah->bt_coex_wlan_weight[1] = AR9300_STOMP_NONE_WLAN_WGHT1;

		break;



	default:

		ath_dbg(ath9k_hw_common(ah), ATH_DBG_BTCOEX,

				"Invalid Stomptype\n");

		break;

	struct ath_btcoex_hw *btcoex = &ah->btcoex_hw;

	const u32 *weight = AR_SREV_9462(ah) ? ar9003_wlan_weights[stomp_type] :

					       ar9462_wlan_weights[stomp_type];

	int i;



	for (i = 0; i < AR9300_NUM_WLAN_WEIGHTS; i++) {

		btcoex->bt_weight[i] = AR9300_BT_WGHT;

		btcoex->wlan_weight[i] = weight[i];

	}



	ath9k_hw_btcoex_enable(ah);

}



/*
@@ -301,7 +316,5 @@ void ath9k_hw_btcoex_bt_stomp(struct ath_hw *ah, 
				"Invalid Stomptype\n");

		break;

	}



	ath9k_hw_btcoex_enable(ah);

}

EXPORT_SYMBOL(ath9k_hw_btcoex_bt_stomp);