[ARM] omap: move propagate_rate() calls into generic omap clock code (9a5fedac) · Commits · e / devices / android_kernel_fairphone_FP3

arch/arm/mach-omap1/clock.c

+0 −6

Original line number	Original line	Diff line number	Diff line
	@@ -244,9 +244,6 @@ static void omap1_ckctl_recalc(struct clk * clk)
	if (unlikely(clk->rate == clk->parent->rate / dsor))		if (unlikely(clk->rate == clk->parent->rate / dsor))
	return; /* No change, quick exit */		return; /* No change, quick exit */
	clk->rate = clk->parent->rate / dsor;		clk->rate = clk->parent->rate / dsor;

	if (unlikely(clk->flags & RATE_PROPAGATES))
	propagate_rate(clk);
	}		}

	static void omap1_ckctl_recalc_dsp_domain(struct clk * clk)		static void omap1_ckctl_recalc_dsp_domain(struct clk * clk)
	@@ -267,9 +264,6 @@ static void omap1_ckctl_recalc_dsp_domain(struct clk * clk)
	if (unlikely(clk->rate == clk->parent->rate / dsor))		if (unlikely(clk->rate == clk->parent->rate / dsor))
	return; /* No change, quick exit */		return; /* No change, quick exit */
	clk->rate = clk->parent->rate / dsor;		clk->rate = clk->parent->rate / dsor;

	if (unlikely(clk->flags & RATE_PROPAGATES))
	propagate_rate(clk);
	}		}

	/* MPU virtual clock functions */		/* MPU virtual clock functions */

arch/arm/mach-omap2/clock.c

+0 −6

Original line number	Original line	Diff line number	Diff line
	@@ -167,9 +167,6 @@ void omap2_fixed_divisor_recalc(struct clk *clk)
	WARN_ON(!clk->fixed_div);		WARN_ON(!clk->fixed_div);

	clk->rate = clk->parent->rate / clk->fixed_div;		clk->rate = clk->parent->rate / clk->fixed_div;

	if (clk->flags & RATE_PROPAGATES)
	propagate_rate(clk);
	}		}

	/**		/**
	@@ -392,9 +389,6 @@ void omap2_clksel_recalc(struct clk *clk)
	clk->rate = clk->parent->rate / div;		clk->rate = clk->parent->rate / div;

	pr_debug("clock: new clock rate is %ld (div %d)\n", clk->rate, div);		pr_debug("clock: new clock rate is %ld (div %d)\n", clk->rate, div);

	if (unlikely(clk->flags & RATE_PROPAGATES))
	propagate_rate(clk);
	}		}

	/**		/**

arch/arm/mach-omap2/clock24xx.c

+2 −4

Original line number	Original line	Diff line number	Diff line
	@@ -199,8 +199,6 @@ long omap2_dpllcore_round_rate(unsigned long target_rate)
	static void omap2_dpllcore_recalc(struct clk *clk)		static void omap2_dpllcore_recalc(struct clk *clk)
	{		{
	clk->rate = omap2_get_dpll_rate_24xx(clk);		clk->rate = omap2_get_dpll_rate_24xx(clk);

	propagate_rate(clk);
	}		}

	static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)		static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
	@@ -442,13 +440,11 @@ static u32 omap2_get_sysclkdiv(void)
	static void omap2_osc_clk_recalc(struct clk *clk)		static void omap2_osc_clk_recalc(struct clk *clk)
	{		{
	clk->rate = omap2_get_apll_clkin() * omap2_get_sysclkdiv();		clk->rate = omap2_get_apll_clkin() * omap2_get_sysclkdiv();
	propagate_rate(clk);
	}		}

	static void omap2_sys_clk_recalc(struct clk *clk)		static void omap2_sys_clk_recalc(struct clk *clk)
	{		{
	clk->rate = clk->parent->rate / omap2_get_sysclkdiv();		clk->rate = clk->parent->rate / omap2_get_sysclkdiv();
	propagate_rate(clk);
	}		}

	/*		/*
	@@ -502,7 +498,9 @@ int __init omap2_clk_init(void)
	clk_init(&omap2_clk_functions);		clk_init(&omap2_clk_functions);

	omap2_osc_clk_recalc(&osc_ck);		omap2_osc_clk_recalc(&osc_ck);
			propagate_rate(&osc_ck);
	omap2_sys_clk_recalc(&sys_ck);		omap2_sys_clk_recalc(&sys_ck);
			propagate_rate(&sys_ck);

	for (clkp = onchip_24xx_clks;		for (clkp = onchip_24xx_clks;
	clkp < onchip_24xx_clks + ARRAY_SIZE(onchip_24xx_clks);		clkp < onchip_24xx_clks + ARRAY_SIZE(onchip_24xx_clks);

arch/arm/mach-omap2/clock24xx.h

+0 −4

Original line number	Original line	Diff line number	Diff line
	@@ -624,7 +624,6 @@ static struct clk func_32k_ck = {
	.flags = CLOCK_IN_OMAP242X \| CLOCK_IN_OMAP243X \|		.flags = CLOCK_IN_OMAP242X \| CLOCK_IN_OMAP243X \|
	RATE_FIXED \| RATE_PROPAGATES,		RATE_FIXED \| RATE_PROPAGATES,
	.clkdm_name = "wkup_clkdm",		.clkdm_name = "wkup_clkdm",
	.recalc = &propagate_rate,
	};		};

	/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */		/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
	@@ -655,7 +654,6 @@ static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
	.flags = CLOCK_IN_OMAP242X \| CLOCK_IN_OMAP243X \|		.flags = CLOCK_IN_OMAP242X \| CLOCK_IN_OMAP243X \|
	RATE_FIXED \| RATE_PROPAGATES,		RATE_FIXED \| RATE_PROPAGATES,
	.clkdm_name = "wkup_clkdm",		.clkdm_name = "wkup_clkdm",
	.recalc = &propagate_rate,
	};		};

	/*		/*
	@@ -702,7 +700,6 @@ static struct clk apll96_ck = {
	.clkdm_name = "wkup_clkdm",		.clkdm_name = "wkup_clkdm",
	.enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),		.enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
	.enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,		.enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
	.recalc = &propagate_rate,
	};		};

	static struct clk apll54_ck = {		static struct clk apll54_ck = {
	@@ -715,7 +712,6 @@ static struct clk apll54_ck = {
	.clkdm_name = "wkup_clkdm",		.clkdm_name = "wkup_clkdm",
	.enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),		.enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
	.enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,		.enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
	.recalc = &propagate_rate,
	};		};

	/*		/*

arch/arm/mach-omap2/clock34xx.c

+0 −5

Original line number	Original line	Diff line number	Diff line
	@@ -57,8 +57,6 @@ static const struct clkops clkops_noncore_dpll_ops;
	static void omap3_dpll_recalc(struct clk *clk)		static void omap3_dpll_recalc(struct clk *clk)
	{		{
	clk->rate = omap2_get_dpll_rate(clk);		clk->rate = omap2_get_dpll_rate(clk);

	propagate_rate(clk);
	}		}

	/* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */		/* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
	@@ -388,9 +386,6 @@ static void omap3_clkoutx2_recalc(struct clk *clk)
	clk->rate = clk->parent->rate;		clk->rate = clk->parent->rate;
	else		else
	clk->rate = clk->parent->rate * 2;		clk->rate = clk->parent->rate * 2;

	if (clk->flags & RATE_PROPAGATES)
	propagate_rate(clk);
	}		}

	/* Common clock code */		/* Common clock code */