Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 9a1683d1 authored by Paul Mundt's avatar Paul Mundt
Browse files

sh: clkfwk: Kill off unused clk_set_rate_ex(). 



With the refactoring of the SH7722 clock framework some time ago this
abstraction has become unecessary. Kill it off before anyone else gets
the bright idea to start using it.

Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent ed10b490

Documentation/DocBook/sh.tmpl

+0 −4
Original line number Diff line number Diff line
@@ -79,10 +79,6 @@ 
      </sect2>

    </sect1>

  </chapter>

  <chapter id="clk">

    <title>Clock Framework Extensions</title>

!Iinclude/linux/sh_clk.h

  </chapter>

  <chapter id="mach">

    <title>Machine Specific Interfaces</title>

    <sect1 id="dreamcast">

Documentation/sh/clk.txt

deleted100644 → 0
+0 −32
Original line number Diff line number Diff line 
Clock framework on SuperH architecture



The framework on SH extends existing API by the function clk_set_rate_ex,

which prototype is as follows:



    clk_set_rate_ex (struct clk *clk, unsigned long rate, int algo_id)



The algo_id parameter is used to specify algorithm used to recalculate clocks,

adjanced to clock, specified as first argument. It is assumed that algo_id==0

means no changes to adjanced clock



Internally, the clk_set_rate_ex forwards request to clk->ops->set_rate method,

if it is present in ops structure. The method should set the clock rate and adjust

all needed clocks according to the passed algo_id.

Exact values for algo_id are machine-dependent. For the sh7722, the following

values are defined:



	NO_CHANGE	= 0,

	IUS_N1_N1,	/* I:U = N:1, U:Sh = N:1 */

	IUS_322,	/* I:U:Sh = 3:2:2	 */

	IUS_522,	/* I:U:Sh = 5:2:2 	 */

	IUS_N11,	/* I:U:Sh = N:1:1	 */

	SB_N1,		/* Sh:B = N:1		 */

	SB3_N1,		/* Sh:B3 = N:1		 */

	SB3_32,		/* Sh:B3 = 3:2		 */

	SB3_43,		/* Sh:B3 = 4:3		 */

	SB3_54,		/* Sh:B3 = 5:4		 */

	BP_N1,		/* B:P	 = N:1		 */

	IP_N1		/* I:P	 = N:1		 */



Each of these constants means relation between clocks that can be set via the FRQCR

register

drivers/sh/clk/core.c

+3 −9
Original line number Diff line number Diff line
@@ -454,12 +454,6 @@ unsigned long clk_get_rate(struct clk *clk) 
EXPORT_SYMBOL_GPL(clk_get_rate);



int clk_set_rate(struct clk *clk, unsigned long rate)

{

	return clk_set_rate_ex(clk, rate, 0);

}

EXPORT_SYMBOL_GPL(clk_set_rate);



int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id)

{

	int ret = -EOPNOTSUPP;

	unsigned long flags;
@@ -467,7 +461,7 @@ int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id) 
	spin_lock_irqsave(&clock_lock, flags);



	if (likely(clk->ops && clk->ops->set_rate)) {

		ret = clk->ops->set_rate(clk, rate, algo_id);

		ret = clk->ops->set_rate(clk, rate, 0);

		if (ret != 0)

			goto out_unlock;

	} else {
@@ -485,7 +479,7 @@ int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id) 


	return ret;

}

EXPORT_SYMBOL_GPL(clk_set_rate_ex);

EXPORT_SYMBOL_GPL(clk_set_rate);



int clk_set_parent(struct clk *clk, struct clk *parent)

{
@@ -654,7 +648,7 @@ static int clks_sysdev_suspend(struct sys_device *dev, pm_message_t state) 
						clkp->parent);

				if (likely(clkp->ops->set_rate))

					clkp->ops->set_rate(clkp,

						rate, NO_CHANGE);

						rate, 0);

				else if (likely(clkp->ops->recalc))

					clkp->rate = clkp->ops->recalc(clkp);

			}

include/linux/sh_clk.h

+0 −30
Original line number Diff line number Diff line
@@ -67,36 +67,6 @@ int clk_register(struct clk *); 
void clk_unregister(struct clk *);

void clk_enable_init_clocks(void);



/**

 * clk_set_rate_ex - set the clock rate for a clock source, with additional parameter

 * @clk: clock source

 * @rate: desired clock rate in Hz

 * @algo_id: algorithm id to be passed down to ops->set_rate

 *

 * Returns success (0) or negative errno.

 */

int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id);



enum clk_sh_algo_id {

	NO_CHANGE = 0,



	IUS_N1_N1,

	IUS_322,

	IUS_522,

	IUS_N11,



	SB_N1,



	SB3_N1,

	SB3_32,

	SB3_43,

	SB3_54,



	BP_N1,



	IP_N1,

};



struct clk_div_mult_table {

	unsigned int *divisors;

	unsigned int nr_divisors;