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Commit 998732dd authored by Taniya Das's avatar Taniya Das
Browse files

clk: qcom: gcc-sdxpoorwills: Remove clock flags for RCGs 



Remove the clock flag which would try to propagate the rate to the
fixed clock sources of the RCG.

Also fix the cpuss and rbcpr clocks to vote on active only clock of XO and
voltage regulator.

Change-Id: I34278e151cd0bc59ca1d258bea49694f22fdd7f1
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent 34e1614a

drivers/clk/qcom/gcc-sdxpoorwills.c

+31 −41
Original line number Diff line number Diff line
@@ -40,6 +40,7 @@ 
#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }



static DEFINE_VDD_REGULATORS(vdd_cx, VDD_CX_NUM, 1, vdd_corner);

static DEFINE_VDD_REGULATORS(vdd_cx_ao, VDD_CX_NUM, 1, vdd_corner);



enum {

	P_BI_TCXO,
@@ -64,6 +65,13 @@ static const char * const gcc_parent_names_0[] = { 
	"core_bi_pll_test_se",

};



static const char * const gcc_parent_names_ao_0[] = {

	"bi_tcxo_ao",

	"gpll0",

	"gpll0_out_even",

	"core_bi_pll_test_se",

};



static const struct parent_map gcc_parent_map_1[] = {

	{ P_BI_TCXO, 0 },

	{ P_CORE_BI_PLL_TEST_SE, 7 },
@@ -219,7 +227,6 @@ static struct clk_rcg2 gcc_blsp1_qup1_i2c_apps_clk_src = { 
		.name = "gcc_blsp1_qup1_i2c_apps_clk_src",

		.parent_names = gcc_parent_names_0,

		.num_parents = 4,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		VDD_CX_FMAX_MAP3(

			MIN, 9600000,
@@ -250,7 +257,6 @@ static struct clk_rcg2 gcc_blsp1_qup1_spi_apps_clk_src = { 
		.name = "gcc_blsp1_qup1_spi_apps_clk_src",

		.parent_names = gcc_parent_names_0,

		.num_parents = 4,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		VDD_CX_FMAX_MAP4(

			MIN, 9600000,
@@ -270,7 +276,6 @@ static struct clk_rcg2 gcc_blsp1_qup2_i2c_apps_clk_src = { 
		.name = "gcc_blsp1_qup2_i2c_apps_clk_src",

		.parent_names = gcc_parent_names_0,

		.num_parents = 4,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		VDD_CX_FMAX_MAP3(

			MIN, 9600000,
@@ -289,7 +294,6 @@ static struct clk_rcg2 gcc_blsp1_qup2_spi_apps_clk_src = { 
		.name = "gcc_blsp1_qup2_spi_apps_clk_src",

		.parent_names = gcc_parent_names_0,

		.num_parents = 4,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		VDD_CX_FMAX_MAP4(

			MIN, 9600000,
@@ -309,7 +313,6 @@ static struct clk_rcg2 gcc_blsp1_qup3_i2c_apps_clk_src = { 
		.name = "gcc_blsp1_qup3_i2c_apps_clk_src",

		.parent_names = gcc_parent_names_0,

		.num_parents = 4,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		VDD_CX_FMAX_MAP3(

			MIN, 9600000,
@@ -328,7 +331,6 @@ static struct clk_rcg2 gcc_blsp1_qup3_spi_apps_clk_src = { 
		.name = "gcc_blsp1_qup3_spi_apps_clk_src",

		.parent_names = gcc_parent_names_0,

		.num_parents = 4,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		VDD_CX_FMAX_MAP4(

			MIN, 9600000,
@@ -348,7 +350,6 @@ static struct clk_rcg2 gcc_blsp1_qup4_i2c_apps_clk_src = { 
		.name = "gcc_blsp1_qup4_i2c_apps_clk_src",

		.parent_names = gcc_parent_names_0,

		.num_parents = 4,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		VDD_CX_FMAX_MAP3(

			MIN, 9600000,
@@ -367,7 +368,6 @@ static struct clk_rcg2 gcc_blsp1_qup4_spi_apps_clk_src = { 
		.name = "gcc_blsp1_qup4_spi_apps_clk_src",

		.parent_names = gcc_parent_names_0,

		.num_parents = 4,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		VDD_CX_FMAX_MAP4(

			MIN, 9600000,
@@ -418,7 +418,6 @@ static struct clk_rcg2 gcc_blsp1_uart1_apps_clk_src = { 
		.name = "gcc_blsp1_uart1_apps_clk_src",

		.parent_names = gcc_parent_names_0,

		.num_parents = 4,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		VDD_CX_FMAX_MAP4(

			MIN, 9600000,
@@ -438,7 +437,6 @@ static struct clk_rcg2 gcc_blsp1_uart2_apps_clk_src = { 
		.name = "gcc_blsp1_uart2_apps_clk_src",

		.parent_names = gcc_parent_names_0,

		.num_parents = 4,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		VDD_CX_FMAX_MAP4(

			MIN, 9600000,
@@ -458,7 +456,6 @@ static struct clk_rcg2 gcc_blsp1_uart3_apps_clk_src = { 
		.name = "gcc_blsp1_uart3_apps_clk_src",

		.parent_names = gcc_parent_names_0,

		.num_parents = 4,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		VDD_CX_FMAX_MAP4(

			MIN, 9600000,
@@ -478,7 +475,6 @@ static struct clk_rcg2 gcc_blsp1_uart4_apps_clk_src = { 
		.name = "gcc_blsp1_uart4_apps_clk_src",

		.parent_names = gcc_parent_names_0,

		.num_parents = 4,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		VDD_CX_FMAX_MAP4(

			MIN, 9600000,
@@ -490,9 +486,6 @@ static struct clk_rcg2 gcc_blsp1_uart4_apps_clk_src = { 


static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {

	F(19200000, P_BI_TCXO, 1, 0, 0),

	F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),

	F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),

	F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),

	{ }

};
@@ -504,21 +497,16 @@ static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { 
	.freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_cpuss_ahb_clk_src",

		.parent_names = gcc_parent_names_0,

		.parent_names = gcc_parent_names_ao_0,

		.num_parents = 4,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		VDD_CX_FMAX_MAP4(

			MIN, 19200000,

			LOWER, 50000000,

			NOMINAL, 100000000,

			HIGH, 133333333),

		VDD_CX_FMAX_MAP1_AO(

				MIN, 19200000),

	},

};



static const struct freq_tbl ftbl_gcc_cpuss_rbcpr_clk_src[] = {

	F(19200000, P_BI_TCXO, 1, 0, 0),

	F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),

	{ }

};
@@ -530,13 +518,11 @@ static struct clk_rcg2 gcc_cpuss_rbcpr_clk_src = { 
	.freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_cpuss_rbcpr_clk_src",

		.parent_names = gcc_parent_names_0,

		.parent_names = gcc_parent_names_ao_0,

		.num_parents = 4,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		VDD_CX_FMAX_MAP2(

			MIN, 19200000,

			NOMINAL, 50000000),

		VDD_CX_FMAX_MAP1_AO(

			MIN, 19200000),

	},

};
@@ -561,7 +547,6 @@ static struct clk_rcg2 gcc_emac_clk_src = { 
		.name = "gcc_emac_clk_src",

		.parent_names = gcc_parent_names_4,

		.num_parents = 5,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		VDD_CX_FMAX_MAP4(

			MIN, 19200000,
@@ -581,7 +566,6 @@ static struct clk_rcg2 gcc_emac_ptp_clk_src = { 
		.name = "gcc_emac_ptp_clk_src",

		.parent_names = gcc_parent_names_4,

		.num_parents = 5,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		VDD_CX_FMAX_MAP4(

			MIN, 19200000,
@@ -610,7 +594,6 @@ static struct clk_rcg2 gcc_gp1_clk_src = { 
		.name = "gcc_gp1_clk_src",

		.parent_names = gcc_parent_names_2,

		.num_parents = 5,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		VDD_CX_FMAX_MAP4(

			MIN, 19200000,
@@ -630,7 +613,6 @@ static struct clk_rcg2 gcc_gp2_clk_src = { 
		.name = "gcc_gp2_clk_src",

		.parent_names = gcc_parent_names_2,

		.num_parents = 5,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		VDD_CX_FMAX_MAP4(

			MIN, 19200000,
@@ -650,7 +632,6 @@ static struct clk_rcg2 gcc_gp3_clk_src = { 
		.name = "gcc_gp3_clk_src",

		.parent_names = gcc_parent_names_2,

		.num_parents = 5,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		VDD_CX_FMAX_MAP4(

			MIN, 19200000,
@@ -675,7 +656,6 @@ static struct clk_rcg2 gcc_pcie_aux_phy_clk_src = { 
		.name = "gcc_pcie_aux_phy_clk_src",

		.parent_names = gcc_parent_names_3,

		.num_parents = 3,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		VDD_CX_FMAX_MAP1(

			MIN, 19200000),
@@ -698,7 +678,6 @@ static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = { 
		.name = "gcc_pcie_phy_refgen_clk_src",

		.parent_names = gcc_parent_names_0,

		.num_parents = 4,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		VDD_CX_FMAX_MAP2(

			MIN, 19200000,
@@ -723,7 +702,6 @@ static struct clk_rcg2 gcc_pdm2_clk_src = { 
		.name = "gcc_pdm2_clk_src",

		.parent_names = gcc_parent_names_0,

		.num_parents = 4,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		VDD_CX_FMAX_MAP3(

			MIN, 9600000,
@@ -742,7 +720,6 @@ static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { 
		.name = "gcc_sdcc1_apps_clk_src",

		.parent_names = gcc_parent_names_0,

		.num_parents = 4,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		VDD_CX_FMAX_MAP4(

			MIN, 19200000,
@@ -762,7 +739,6 @@ static struct clk_rcg2 gcc_spmi_fetcher_clk_src = { 
		.name = "gcc_spmi_fetcher_clk_src",

		.parent_names = gcc_parent_names_1,

		.num_parents = 2,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		VDD_CX_FMAX_MAP1(

			MIN, 19200000),
@@ -788,7 +764,6 @@ static struct clk_rcg2 gcc_usb30_master_clk_src = { 
		.name = "gcc_usb30_master_clk_src",

		.parent_names = gcc_parent_names_0,

		.num_parents = 4,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		VDD_CX_FMAX_MAP5(

			MIN, 50000000,
@@ -816,7 +791,6 @@ static struct clk_rcg2 gcc_usb30_mock_utmi_clk_src = { 
		.name = "gcc_usb30_mock_utmi_clk_src",

		.parent_names = gcc_parent_names_0,

		.num_parents = 4,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		VDD_CX_FMAX_MAP3(

			MIN, 19200000,
@@ -841,7 +815,6 @@ static struct clk_rcg2 gcc_usb3_phy_aux_clk_src = { 
		.name = "gcc_usb3_phy_aux_clk_src",

		.parent_names = gcc_parent_names_3,

		.num_parents = 3,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		VDD_CX_FMAX_MAP1(

			MIN, 19200000),
@@ -1884,6 +1857,14 @@ static int gcc_sdxpoorwills_probe(struct platform_device *pdev) 
		return PTR_ERR(vdd_cx.regulator[0]);

	}



	vdd_cx_ao.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_cx_ao");

	if (IS_ERR(vdd_cx_ao.regulator[0])) {

		if (!(PTR_ERR(vdd_cx_ao.regulator[0]) == -EPROBE_DEFER))

			dev_err(&pdev->dev,

				"Unable to get vdd_cx_ao regulator\n");

		return PTR_ERR(vdd_cx_ao.regulator[0]);

	}



	/* Register the dummy measurement clocks */

	for (i = 0; i < ARRAY_SIZE(gcc_sdxpoorwills_hws); i++) {

		clk = devm_clk_register(&pdev->dev, gcc_sdxpoorwills_hws[i]);
@@ -1922,6 +1903,15 @@ static void __exit gcc_sdxpoorwills_exit(void) 
}

module_exit(gcc_sdxpoorwills_exit);



static int gcc_cpuss_ahb_clk_update_rate(void)

{

	clk_set_rate(gcc_cpuss_ahb_clk.clkr.hw.clk, 19200000);

	clk_set_rate(gcc_sys_noc_cpuss_ahb_clk.clkr.hw.clk, 19200000);



	return 0;

}

late_initcall(gcc_cpuss_ahb_clk_update_rate);



MODULE_DESCRIPTION("QTI GCC SDXPOORWILLS Driver");

MODULE_LICENSE("GPL v2");

MODULE_ALIAS("platform:gcc-sdxpoorwills");