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Commit 996f545f authored by Alexandre Courbot's avatar Alexandre Courbot Committed by Ben Skeggs
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drm/nouveau/gem: allow user-space to specify an object should be coherent 



User-space use mappable BOs notably for fences, and expects that a
value update by the GPU will be immediatly visible through the
user-space mapping.

ARM has a property that may prevent this from happening though: memory
can be mapped multiple times only if the different mappings share the
same caching properties. However all the lowmem memory is already
identity-mapped into the kernel with cache enabled, so when user-space
requests an uncached mapping, we actually get an "undefined caching
policy" one and this has strange side-effects described on Freedesktop
bug 86690.

To prevent this from happening, allow user-space to explicitly specify
which objects should be coherent, and create such objects with the
TTM_PL_FLAG_UNCACHED flag. This will make TTM allocate memory using the
DMA API, which will fix the identify mapping and allow us to safely map
the objects to user-space uncached.

Signed-off-by: default avatarAlexandre Courbot <acourbot@nvidia.com>
Reviewed-by: default avatarLucas Stach <dev@lynxeye.de>
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent a7f6da6e

drivers/gpu/drm/nouveau/nouveau_gem.c

+3 −0
Original line number Original line Diff line number Diff line
@@ -189,6 +189,9 @@ nouveau_gem_new(struct drm_device *dev, int size, int align, uint32_t domain, 
	if (!flags || domain & NOUVEAU_GEM_DOMAIN_CPU)

	if (!flags || domain & NOUVEAU_GEM_DOMAIN_CPU)

		flags |= TTM_PL_FLAG_SYSTEM;

		flags |= TTM_PL_FLAG_SYSTEM;





	if (domain & NOUVEAU_GEM_DOMAIN_COHERENT)

		flags |= TTM_PL_FLAG_UNCACHED;



	ret = nouveau_bo_new(dev, size, align, flags, tile_mode,

	ret = nouveau_bo_new(dev, size, align, flags, tile_mode,

			     tile_flags, NULL, NULL, pnvbo);

			     tile_flags, NULL, NULL, pnvbo);

	if (ret)

	if (ret)

include/uapi/drm/nouveau_drm.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -39,6 +39,7 @@ 
#define NOUVEAU_GEM_DOMAIN_VRAM      (1 << 1)

#define NOUVEAU_GEM_DOMAIN_VRAM      (1 << 1)

#define NOUVEAU_GEM_DOMAIN_GART      (1 << 2)

#define NOUVEAU_GEM_DOMAIN_GART      (1 << 2)

#define NOUVEAU_GEM_DOMAIN_MAPPABLE  (1 << 3)

#define NOUVEAU_GEM_DOMAIN_MAPPABLE  (1 << 3)

#define NOUVEAU_GEM_DOMAIN_COHERENT  (1 << 4)





#define NOUVEAU_GEM_TILE_COMP        0x00030000 /* nv50-only */

#define NOUVEAU_GEM_TILE_COMP        0x00030000 /* nv50-only */

#define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00

#define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00