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Commit 9863aba5 authored by Fugang Duan's avatar Fugang Duan Committed by Shawn Guo
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ARM: dts: imx6x: Add enet2 support for imx6sx-sdb board 



Add enet2 support for imx6sx-sdb board, and add the "fsl,imx6q-fec"
compatible for fec2 node to be compatible with the old version.

Signed-off-by: default avatarFugang Duan <B38611@freescale.com>
Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
parent 791f4166

arch/arm/boot/dts/imx6sx-sdb.dts

+62 −0
Original line number Diff line number Diff line
@@ -105,6 +105,30 @@ 
			gpio = <&gpio3 27 0>;

			enable-active-high;

		};



		reg_peri_3v3: regulator@5 {

			compatible = "regulator-fixed";

			reg = <5>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_peri_3v3>;

			regulator-name = "peri_3v3";

			regulator-min-microvolt = <3300000>;

			regulator-max-microvolt = <3300000>;

			gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;

			enable-active-high;

			regulator-always-on;

		};



		reg_enet_3v3: regulator@6 {

			compatible = "regulator-fixed";

			reg = <6>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_enet_3v3>;

			regulator-name = "enet_3v3";

			regulator-min-microvolt = <3300000>;

			regulator-max-microvolt = <3300000>;

			gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;

		};

	};



	sound {
@@ -133,6 +157,14 @@ 
&fec1 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_enet1>;

	phy-supply = <&reg_enet_3v3>;

	phy-mode = "rgmii";

	status = "okay";

};



&fec2 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_enet2>;

	phy-mode = "rgmii";

	status = "okay";

};
@@ -394,6 +426,30 @@ 
				MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2	0x3081

				MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3	0x3081

				MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN	0x3081

				MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M	0x91

			>;

		};



		pinctrl_enet_3v3: enet3v3grp {

			fsl,pins = <

				MX6SX_PAD_ENET2_COL__GPIO2_IO_6		0x80000000

			>;

		};



		pinctrl_enet2: enet2grp {

			fsl,pins = <

				MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC	0xa0b9

				MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0	0xa0b1

				MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1	0xa0b1

				MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2	0xa0b1

				MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3	0xa0b1

				MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN	0xa0b1

				MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK	0x3081

				MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0	0x3081

				MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1	0x3081

				MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2	0x3081

				MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3	0x3081

				MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN	0x3081

			>;

		};
@@ -452,6 +508,12 @@ 
			>;

		};



		pinctrl_peri_3v3: peri3v3grp {

			fsl,pins = <

				MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16	0x80000000

			>;

		};



		pinctrl_pwm3: pwm3grp-1 {

			fsl,pins = <

				MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0

arch/arm/boot/dts/imx6sx.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -877,7 +877,7 @@ 
			};



			fec2: ethernet@021b4000 {

				compatible = "fsl,imx6sx-fec";

				compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";

				reg = <0x021b4000 0x4000>;

				interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;