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Commit 982cb329 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/radeon: clarify family checks in pm table parsing 



We actually care about the chip family rather than the
DCE version although functionally they are the same.

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent facd112d

drivers/gpu/drm/radeon/radeon_atombios.c

+3 −3
Original line number Original line Diff line number Diff line
@@ -2309,7 +2309,7 @@ static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rde 
		rdev->pm.default_power_state_index = state_index;

		rdev->pm.default_power_state_index = state_index;

		rdev->pm.power_state[state_index].default_clock_mode =

		rdev->pm.power_state[state_index].default_clock_mode =

			&rdev->pm.power_state[state_index].clock_info[mode_index - 1];

			&rdev->pm.power_state[state_index].clock_info[mode_index - 1];

		if (ASIC_IS_DCE5(rdev) && !(rdev->flags & RADEON_IS_IGP)) {

		if ((rdev->family >= CHIP_BARTS) && !(rdev->flags & RADEON_IS_IGP)) {

			/* NI chips post without MC ucode, so default clocks are strobe mode only */

			/* NI chips post without MC ucode, so default clocks are strobe mode only */

			rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;

			rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;

			rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;

			rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
@@ -2347,7 +2347,7 @@ static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev, 
			sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;

			sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;

			rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;

			rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;

		}

		}

	} else if (ASIC_IS_DCE6(rdev)) {

	} else if (rdev->family >= CHIP_TAHITI) {

		sclk = le16_to_cpu(clock_info->si.usEngineClockLow);

		sclk = le16_to_cpu(clock_info->si.usEngineClockLow);

		sclk |= clock_info->si.ucEngineClockHigh << 16;

		sclk |= clock_info->si.ucEngineClockHigh << 16;

		mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);

		mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
@@ -2360,7 +2360,7 @@ static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev, 
			le16_to_cpu(clock_info->si.usVDDC);

			le16_to_cpu(clock_info->si.usVDDC);

		rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =

		rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =

			le16_to_cpu(clock_info->si.usVDDCI);

			le16_to_cpu(clock_info->si.usVDDCI);

	} else if (ASIC_IS_DCE4(rdev)) {

	} else if (rdev->family >= CHIP_CEDAR) {

		sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);

		sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);

		sclk |= clock_info->evergreen.ucEngineClockHigh << 16;

		sclk |= clock_info->evergreen.ucEngineClockHigh << 16;

		mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);

		mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);