Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 97ed465b authored by Wenyou Yang's avatar Wenyou Yang Committed by Mark Brown
Browse files

spi/spi-atmel: add support transfer on CS1,2,3, not only on CS0

parent d4820b74
Loading
Loading
Loading
Loading
+12 −13
Original line number Diff line number Diff line
@@ -255,11 +255,6 @@ static bool atmel_spi_is_v2(struct atmel_spi *as)
 * Master on Chip Select 0.")  No workaround exists for that ... so for
 * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
 * and (c) will trigger that first erratum in some cases.
 *
 * TODO: Test if the atmel_spi_is_v2() branch below works on
 * AT91RM9200 if we use some other register than CSR0. However, don't
 * do this unconditionally since AP7000 has an errata where the BITS
 * field in CSR0 overrides all other CSRs.
 */

static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
@@ -269,17 +264,21 @@ static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
	u32 mr;

	if (atmel_spi_is_v2(as)) {
		/*
		 * Always use CSR0. This ensures that the clock
		 * switches to the correct idle polarity before we
		 * toggle the CS.
		spi_writel(as, CSR0 + 4 * spi->chip_select, asd->csr);
		/* For the low SPI version, there is a issue that PDC transfer
		 * on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS
		 */
		spi_writel(as, CSR0, asd->csr);
		if (as->caps.has_wdrbt) {
			spi_writel(as, MR, SPI_BF(PCS, 0x0e) | SPI_BIT(WDRBT)
				| SPI_BIT(MODFDIS) | SPI_BIT(MSTR));
			spi_writel(as, MR,
					SPI_BF(PCS, ~(0x01 << spi->chip_select))
					| SPI_BIT(WDRBT)
					| SPI_BIT(MODFDIS)
					| SPI_BIT(MSTR));
		} else {
			spi_writel(as, MR, SPI_BF(PCS, 0x0e) | SPI_BIT(MODFDIS)
			spi_writel(as, MR,
					SPI_BF(PCS, ~(0x01 << spi->chip_select))
					| SPI_BIT(MODFDIS)
					| SPI_BIT(MSTR));
		}
		mr = spi_readl(as, MR);