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Commit 97c8e6a0 authored by Deepak Katragadda's avatar Deepak Katragadda Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Add speedbin2 CPU clock frequency support for SDM845 v2 



Update the speedbin table for the CPU clocks on SDM845 v2 in order
to support the new speedbin 2 frequencies.

Change-Id: I4bd036c79884b76529318e5cbaaad682003a72bd
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent d6f4899a

arch/arm64/boot/dts/qcom/sdm845-v2.dtsi

+76 −0
Original line number Diff line number Diff line
@@ -753,6 +753,23 @@ 
		<  1497600000 0x403c0d4e 0x00003e3e 0x2 14 >,

		<  1593600000 0x403c0e53 0x00004242 0x2 15 >;



	qcom,l3-speedbin2-v0 =

		<   300000000 0x000c000f 0x00002020 0x1 1 >,

		<   403200000 0x500c0115 0x00002020 0x1 2 >,

		<   480000000 0x50140219 0x00002020 0x1 3 >,

		<   576000000 0x5014031e 0x00002020 0x1 4 >,

		<   652800000 0x401c0422 0x00002020 0x1 5 >,

		<   748800000 0x401c0527 0x00002020 0x1 6 >,

		<   844800000 0x4024062c 0x00002323 0x2 7 >,

		<   940800000 0x40240731 0x00002727 0x2 8 >,

		<  1036800000 0x40240836 0x00002b2b 0x2 9 >,

		<  1132800000 0x402c093b 0x00002f2f 0x2 10 >,

		<  1209600000 0x402c0a3f 0x00003232 0x2 11 >,

		<  1305600000 0x40340b44 0x00003636 0x2 12 >,

		<  1401600000 0x40340c49 0x00003a3a 0x2 13 >,

		<  1497600000 0x403c0d4e 0x00003e3e 0x2 14 >,

		<  1593600000 0x403c0e53 0x00004242 0x2 15 >;



	qcom,pwrcl-speedbin0-v0 =

		<   300000000 0x000c000f 0x00002020 0x1 1 >,

		<   403200000 0x500c0115 0x00002020 0x1 2 >,
@@ -793,6 +810,26 @@ 
		<  1689600000 0x40441058 0x00004646 0x2 17 >,

		<  1766400000 0x4044115c 0x00004a4a 0x2 18 >;



	qcom,pwrcl-speedbin2-v0 =

		<   300000000 0x000c000f 0x00002020 0x1 1 >,

		<   403200000 0x500c0115 0x00002020 0x1 2 >,

		<   480000000 0x50140219 0x00002020 0x1 3 >,

		<   576000000 0x5014031e 0x00002020 0x1 4 >,

		<   652800000 0x401c0422 0x00002020 0x1 5 >,

		<   748800000 0x401c0527 0x00002020 0x1 6 >,

		<   825600000 0x401c062b 0x00002222 0x1 7 >,

		<   902400000 0x4024072f 0x00002626 0x1 8 >,

		<   979200000 0x40240833 0x00002929 0x1 9 >,

		<  1056000000 0x402c0937 0x00002c2c 0x2 10 >,

		<  1132800000 0x402c0a3b 0x00002f2f 0x2 11 >,

		<  1228800000 0x402c0b40 0x00003333 0x2 12 >,

		<  1324800000 0x40340c45 0x00003737 0x2 13 >,

		<  1420800000 0x40340d4a 0x00003b3b 0x2 14 >,

		<  1516800000 0x403c0e4f 0x00003f3f 0x2 15 >,

		<  1612800000 0x403c0f54 0x00004343 0x2 16 >,

		<  1689600000 0x40441058 0x00004646 0x2 17 >,

		<  1766400000 0x4044115c 0x00004a4a 0x2 18 >;



	qcom,perfcl-speedbin0-v0 =

		<   300000000 0x000c000f 0x00002020 0x1 1 >,

		<   403200000 0x500c0115 0x00002020 0x1 2 >,
@@ -855,14 +892,53 @@ 
		<  2649600000 0x40541d8a 0x00006e6e 0x2 30 >,

		<  2745600000 0x40511e8f 0x00007272 0x2 31 >;



	qcom,perfcl-speedbin2-v0 =

		<   300000000 0x000c000f 0x00002020 0x1 1 >,

		<   403200000 0x500c0115 0x00002020 0x1 2 >,

		<   480000000 0x50140219 0x00002020 0x1 3 >,

		<   576000000 0x5014031e 0x00002020 0x1 4 >,

		<   652800000 0x401c0422 0x00002020 0x1 5 >,

		<   748800000 0x401c0527 0x00002020 0x1 6 >,

		<   825600000 0x401c062b 0x00002222 0x1 7 >,

		<   902400000 0x4024072f 0x00002626 0x1 8 >,

		<   979200000 0x40240833 0x00002929 0x1 9 >,

		<  1056000000 0x402c0937 0x00002c2c 0x1 10 >,

		<  1132800000 0x402c0a3b 0x00002f2f 0x1 11 >,

		<  1209600000 0x402c0b3f 0x00003232 0x2 12 >,

		<  1286400000 0x40340c43 0x00003636 0x2 13 >,

		<  1363200000 0x40340d47 0x00003939 0x2 14 >,

		<  1459200000 0x403c0e4c 0x00003d3d 0x2 15 >,

		<  1536000000 0x403c0f50 0x00004040 0x2 16 >,

		<  1612800000 0x403c1054 0x00004343 0x2 17 >,

		<  1689600000 0x40441158 0x00004646 0x2 18 >,

		<  1766400000 0x4044125c 0x00004a4a 0x2 19 >,

		<  1843200000 0x40441360 0x00004d4d 0x2 20 >,

		<  1920000000 0x404c1464 0x00005050 0x2 21 >,

		<  1996800000 0x404c1568 0x00005353 0x2 22 >,

		<  2092800000 0x4054166d 0x00005757 0x2 23 >,

		<  2169600000 0x40541771 0x00005a5a 0x2 24 >,

		<  2246400000 0x40541875 0x00005e5e 0x2 25 >,

		<  2323200000 0x40541979 0x00006161 0x2 26 >,

		<  2400000000 0x40541a7d 0x00006464 0x2 27 >,

		<  2476800000 0x40541b81 0x00006767 0x2 28 >,

		<  2553600000 0x40541c85 0x00006a6a 0x2 29 >,

		<  2649600000 0x40541d8a 0x00006e6e 0x2 30 >,

		<  2707200000 0x40511e8d 0x00007171 0x2 30 >,

		<  2764800000 0x40511f90 0x00007373 0x2 31 >,

		<  2784000000 0x40512091 0x00007474 0x2 32 >,

		<  2803200000 0x40512192 0x00007575 0x2 33 >;



	qcom,l3-memacc-level-vc-bin0 = <8 13>;

	qcom,l3-memacc-level-vc-bin1 = <8 13>;

	qcom,l3-memacc-level-vc-bin2 = <8 13>;



	qcom,pwrcl-memacc-level-vc-bin0 = <12 16>;

	qcom,pwrcl-memacc-level-vc-bin1 = <12 16>;

	qcom,pwrcl-memacc-level-vc-bin2 = <12 16>;



	qcom,perfcl-memacc-level-vc-bin0 = <14 22>;

	qcom,perfcl-memacc-level-vc-bin1 = <14 22>;

	qcom,perfcl-memacc-level-vc-bin2 = <14 22>;

};



&pcie1 {