Merge "drm/msm/sde: Parse lut dma offsets from device tree" into msm-4.8 (978afe89) · Commits · e / devices / android_kernel_fairphone_FP3

Documentation/devicetree/bindings/display/msm/sde.txt

+9 −2

Original line number	Diff line number	Diff line
		@@ -237,6 +237,11 @@ Optional properties:
		control register. Number of offsets defined should
		match the number of offsets defined in
		property: qcom,sde-wb-off
		- qcom,sde-reg-dma-off: Offset of the register dma hardware block from
		"regdma_phys" defined in reg property.
		- qcom,sde-reg-dma-version: Version of the reg dma hardware block.
		- qcom,sde-reg-dma-trigger-off: Offset of the lut dma trigger reg from "mdp_phys"
		defined in reg property.
		Bus Scaling Data:
		- qcom,msm-bus,name: String property describing client name.
		- qcom,msm-bus,num-cases: This is the number of Bus Scaling use cases
		@@ -268,10 +273,12 @@ Example:
		compatible = "qcom,sde-kms";
		reg = <0x00900000 0x90000>,
		<0x009b0000 0x1040>,
		<0x009b8000 0x1040>;
		<0x009b8000 0x1040>,
		<0x0aeac000 0x00f0>;
		reg-names = "mdp_phys",
		"vbif_phys",
		"vbif_nrt_phys";
		"vbif_nrt_phys",
		"regdma_phys";
		clocks = <&clock_mmss clk_mdss_ahb_clk>,
		<&clock_mmss clk_mdss_axi_clk>,
		<&clock_mmss clk_mdp_clk_src>,

drivers/gpu/drm/msm/sde/sde_hw_catalog.c

+54 −0

Original line number	Diff line number	Diff line
		@@ -227,6 +227,13 @@ enum {
		VBIF_PROP_MAX,
		};

		enum {
		REG_DMA_OFF,
		REG_DMA_VERSION,
		REG_DMA_TRIGGER_OFF,
		REG_DMA_PROP_MAX
		};

		/*************************************************************
		* dts property definition
		*************************************************************/
		@@ -406,6 +413,16 @@ static struct sde_prop_type vbif_prop[] = {
		PROP_TYPE_U32_ARRAY},
		};

		static struct sde_prop_type reg_dma_prop[REG_DMA_PROP_MAX] = {
		[REG_DMA_OFF] = {REG_DMA_OFF, "qcom,sde-reg-dma-off", false,
		PROP_TYPE_U32},
		[REG_DMA_VERSION] = {REG_DMA_VERSION, "qcom,sde-reg-dma-version",
		false, PROP_TYPE_U32},
		[REG_DMA_TRIGGER_OFF] = {REG_DMA_TRIGGER_OFF,
		"qcom,sde-reg-dma-trigger-off", false,
		PROP_TYPE_U32},
		};

		/*************************************************************
		* static API list
		*************************************************************/
		@@ -1880,6 +1897,39 @@ static int sde_parse_dt(struct device_node np, struct sde_mdss_cfg cfg)
		return rc;
		}

		static int sde_parse_reg_dma_dt(struct device_node *np,
		struct sde_mdss_cfg *sde_cfg)
		{
		u32 val;
		int rc = 0;
		int i = 0;

		sde_cfg->reg_dma_count = 0;
		for (i = 0; i < REG_DMA_PROP_MAX; i++) {
		rc = of_property_read_u32(np, reg_dma_prop[i].prop_name,
		&val);
		if (rc)
		break;
		switch (i) {
		case REG_DMA_OFF:
		sde_cfg->dma_cfg.base = val;
		break;
		case REG_DMA_VERSION:
		sde_cfg->dma_cfg.version = val;
		break;
		case REG_DMA_TRIGGER_OFF:
		sde_cfg->dma_cfg.trigger_sel_off = val;
		break;
		default:
		break;
		}
		}
		if (!rc && i == REG_DMA_PROP_MAX)
		sde_cfg->reg_dma_count = 1;
		/* reg dma is optional feature hence return 0 */
		return 0;
		}

		static void sde_hardware_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev)
		{
		switch (hw_rev) {
		@@ -1981,6 +2031,10 @@ struct sde_mdss_cfg sde_hw_catalog_init(struct drm_device dev, u32 hw_rev)
		if (rc)
		goto end;

		rc = sde_parse_reg_dma_dt(np, sde_cfg);
		if (rc)
		goto end;

		sde_hardware_caps(sde_cfg, hw_rev);

		return sde_cfg;

drivers/gpu/drm/msm/sde/sde_hw_catalog.h

+16 −0

Original line number	Diff line number	Diff line
		@@ -599,6 +599,19 @@ struct sde_vbif_cfg {
		struct sde_vbif_dynamic_ot_tbl dynamic_ot_rd_tbl;
		struct sde_vbif_dynamic_ot_tbl dynamic_ot_wr_tbl;
		};
		/**
		* struct sde_reg_dma_cfg - information of lut dma blocks
		* @id enum identifying this block
		* @base register offset of this block
		* @features bit mask identifying sub-blocks/features
		* @version version of lutdma hw block
		* @trigger_sel_off offset to trigger select registers of lutdma
		*/
		struct sde_reg_dma_cfg {
		SDE_HW_BLK_INFO;
		u32 version;
		u32 trigger_sel_off;
		};

		/**
		* struct sde_mdss_cfg - information of MDSS HW
		@@ -663,6 +676,9 @@ struct sde_mdss_cfg {

		u32 vbif_count;
		struct sde_vbif_cfg vbif[MAX_BLOCKS];

		u32 reg_dma_count;
		struct sde_reg_dma_cfg dma_cfg;
		/* Add additional block data structures here */
		};