Merge "drm/msm/sde: move current performance setting to crtc object" (970ba0f7) · Commits · e / devices / android_kernel_fairphone_FP3

drivers/gpu/drm/msm/sde/sde_core_perf.c

+5 −7

Original line number	Diff line number	Diff line
		@@ -172,8 +172,7 @@ int sde_core_perf_crtc_check(struct drm_crtc *crtc,

		sde_cstate = to_sde_crtc_state(state);

		/* swap state and obtain new values */
		sde_cstate->cur_perf = sde_cstate->new_perf;
		/* obtain new values */
		_sde_core_perf_calc_crtc(kms, crtc, state, &sde_cstate->new_perf);

		bw_sum_of_intfs = sde_cstate->new_perf.bw_ctl;
		@@ -204,11 +203,9 @@ int sde_core_perf_crtc_check(struct drm_crtc *crtc,
		if (!sde_cstate->bw_control) {
		SDE_DEBUG("bypass bandwidth check\n");
		} else if (!threshold) {
		sde_cstate->new_perf = sde_cstate->cur_perf;
		SDE_ERROR("no bandwidth limits specified\n");
		return -E2BIG;
		} else if (bw > threshold) {
		sde_cstate->new_perf = sde_cstate->cur_perf;
		SDE_ERROR("exceeds bandwidth: %ukb > %ukb\n", bw, threshold);
		return -E2BIG;
		}
		@@ -347,6 +344,7 @@ static void _sde_core_perf_crtc_update_bus(struct sde_kms *kms,
		void sde_core_perf_crtc_release_bw(struct drm_crtc *crtc)
		{
		struct drm_crtc *tmp_crtc;
		struct sde_crtc *sde_crtc;
		struct sde_crtc_state *sde_cstate;
		struct sde_kms *kms;

		@@ -361,6 +359,7 @@ void sde_core_perf_crtc_release_bw(struct drm_crtc *crtc)
		return;
		}

		sde_crtc = to_sde_crtc(crtc);
		sde_cstate = to_sde_crtc_state(crtc->state);

		/* only do this for command mode rt client (non-rsc client) */
		@@ -383,8 +382,7 @@ void sde_core_perf_crtc_release_bw(struct drm_crtc *crtc)
		/* Release the bandwidth */
		if (kms->perf.enable_bw_release) {
		trace_sde_cmd_release_bw(crtc->base.id);
		sde_cstate->cur_perf.bw_ctl = 0;
		sde_cstate->new_perf.bw_ctl = 0;
		sde_crtc->cur_perf.bw_ctl = 0;
		SDE_DEBUG("Release BW crtc=%d\n", crtc->base.id);
		_sde_core_perf_crtc_update_bus(kms, crtc);
		}
		@@ -447,7 +445,7 @@ void sde_core_perf_crtc_update(struct drm_crtc *crtc,
		SDE_DEBUG("crtc:%d stop_req:%d core_clk:%llu\n",
		crtc->base.id, stop_req, kms->perf.core_clk_rate);

		old = &sde_cstate->cur_perf;
		old = &sde_crtc->cur_perf;
		new = &sde_cstate->new_perf;

		if (_sde_core_perf_crtc_is_power_on(crtc) && !stop_req) {

drivers/gpu/drm/msm/sde/sde_crtc.c

+5 −3

Original line number	Diff line number	Diff line
		@@ -3422,16 +3422,18 @@ static const struct file_operations __prefix ## _fops = { \
		static int sde_crtc_debugfs_state_show(struct seq_file s, void v)
		{
		struct drm_crtc crtc = (struct drm_crtc ) s->private;
		struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
		struct sde_crtc_state *cstate = to_sde_crtc_state(crtc->state);
		struct sde_crtc_res *res;

		seq_printf(s, "num_connectors: %d\n", cstate->num_connectors);
		seq_printf(s, "client type: %d\n", sde_crtc_get_client_type(crtc));
		seq_printf(s, "intf_mode: %d\n", sde_crtc_get_intf_mode(crtc));
		seq_printf(s, "bw_ctl: %llu\n", cstate->cur_perf.bw_ctl);
		seq_printf(s, "core_clk_rate: %llu\n", cstate->cur_perf.core_clk_rate);
		seq_printf(s, "bw_ctl: %llu\n", sde_crtc->cur_perf.bw_ctl);
		seq_printf(s, "core_clk_rate: %llu\n",
		sde_crtc->cur_perf.core_clk_rate);
		seq_printf(s, "max_per_pipe_ib: %llu\n",
		cstate->cur_perf.max_per_pipe_ib);
		sde_crtc->cur_perf.max_per_pipe_ib);

		seq_printf(s, "rp.%d: ", cstate->rp.sequence_id);
		list_for_each_entry(res, &cstate->rp.res_list, list)

drivers/gpu/drm/msm/sde/sde_crtc.h

+4 −3

Original line number	Diff line number	Diff line
		@@ -141,6 +141,7 @@ struct sde_crtc_event {
		* @event_lock : Spinlock around event handling code
		* @misr_enable : boolean entry indicates misr enable/disable status.
		* @power_event : registered power event handle
		* @cur_perf : current performance committed to clock/bandwidth driver
		*/
		struct sde_crtc {
		struct drm_crtc base;
		@@ -193,6 +194,8 @@ struct sde_crtc {
		bool misr_enable;

		struct sde_power_event *power_event;

		struct sde_core_perf_params cur_perf;
		};

		#define to_sde_crtc(x) container_of(x, struct sde_crtc, base)
		@@ -268,8 +271,7 @@ struct sde_crtc_respool {
		* @property_blobs: Reference pointers for blob properties
		* @num_dim_layers: Number of dim layers
		* @dim_layer: Dim layer configs
		* @cur_perf: current performance state
		* @new_perf: new performance state
		* @new_perf: new performance state being requested
		* @sbuf_cfg: stream buffer configuration
		* @sbuf_prefill_line: number of line for inline rotator prefetch
		* @sbuf_flush_mask: flush mask for inline rotator
		@@ -296,7 +298,6 @@ struct sde_crtc_state {
		uint32_t num_dim_layers;
		struct sde_hw_dim_layer dim_layer[SDE_MAX_DIM_LAYERS];

		struct sde_core_perf_params cur_perf;
		struct sde_core_perf_params new_perf;
		struct sde_ctl_sbuf_cfg sbuf_cfg;
		u32 sbuf_prefill_line;