Merge tag 'imx-dt-4.1' of...

Freescale Vybrid Miscellaneous System Control - CPU Configuration

The MSCM IP contains multiple sub modules, this binding describes the first

block of registers which contains CPU configuration information.

Required properties:

- compatible:	"fsl,vf610-mscm-cpucfg", "syscon"

- reg:		the register range of the MSCM CPU configuration registers

Example:

	mscm_cpucfg: cpucfg@40001000 {

		compatible = "fsl,vf610-mscm-cpucfg", "syscon";

		reg = <0x40001000 0x800>;

	}

Freescale Vybrid Miscellaneous System Control - Interrupt Router

The MSCM IP contains multiple sub modules, this binding describes the second

block of registers which control the interrupt router. The interrupt router

allows to configure the recipient of each peripheral interrupt. Furthermore

it controls the directed processor interrupts. The module is available in all

Vybrid SoC's but is only really useful in dual core configurations (VF6xx

which comes with a Cortex-A5/Cortex-M4 combination).

Required properties:

- compatible:		"fsl,vf610-mscm-ir"

- reg:			the register range of the MSCM Interrupt Router

- fsl,cpucfg:		The handle to the MSCM CPU configuration node, required

			to get the current CPU ID

- interrupt-controller:	Identifies the node as an interrupt controller

- #interrupt-cells:	Two cells, interrupt number and cells.

			The hardware interrupt number according to interrupt

			assignment of the interrupt router is required.

			Flags get passed only when using GIC as parent. Flags

			encoding as documented by the GIC bindings.

- interrupt-parent:	Should be the phandle for the interrupt controller of

			the CPU the device tree is intended to be used on. This

			is either the node of the GIC or NVIC controller.

Example:

	mscm_ir: interrupt-controller@40001800 {

		compatible = "fsl,vf610-mscm-ir";

		reg = <0x40001800 0x400>;

		fsl,cpucfg = <&mscm_cpucfg>;

		interrupt-controller;

		#interrupt-cells = <2>;

		interrupt-parent = <&intc>;

	}

Freescale i.MX General Power Controller

=======================================

The i.MX6Q General Power Control (GPC) block contains DVFS load tracking

counters and Power Gating Control (PGC) for the CPU and PU (GPU/VPU) power

domains.

Required properties:

- compatible: Should be "fsl,imx6q-gpc" or "fsl,imx6sl-gpc"

- reg: should be register base and length as documented in the

  datasheet

- interrupts: Should contain GPC interrupt request 1

- pu-supply: Link to the LDO regulator powering the PU power domain

- clocks: Clock phandles to devices in the PU power domain that need

	  to be enabled during domain power-up for reset propagation.

- #power-domain-cells: Should be 1, see below:

The gpc node is a power-controller as documented by the generic power domain

bindings in Documentation/devicetree/bindings/power/power_domain.txt.

Example:

	gpc: gpc@020dc000 {

		compatible = "fsl,imx6q-gpc";

		reg = <0x020dc000 0x4000>;

		interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,

			     <0 90 IRQ_TYPE_LEVEL_HIGH>;

		pu-supply = <&reg_pu>;

		clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,

			 <&clks IMX6QDL_CLK_GPU3D_SHADER>,

			 <&clks IMX6QDL_CLK_GPU2D_CORE>,

			 <&clks IMX6QDL_CLK_GPU2D_AXI>,

			 <&clks IMX6QDL_CLK_OPENVG_AXI>,

			 <&clks IMX6QDL_CLK_VPU_AXI>;

		#power-domain-cells = <1>;

	};

Specifying power domain for IP modules

======================================

IP cores belonging to a power domain should contain a 'power-domains' property

that is a phandle pointing to the gpc device node and a DOMAIN_INDEX specifying

the power domain the device belongs to.

Example of a device that is part of the PU power domain:

	vpu: vpu@02040000 {

		reg = <0x02040000 0x3c000>;

		/* ... */

		power-domains = <&gpc 1>;

		/* ... */

	};

The following DOMAIN_INDEX values are valid for i.MX6Q:

ARM_DOMAIN     0

PU_DOMAIN      1

The following additional DOMAIN_INDEX value is valid for i.MX6SL:

DISPLAY_DOMAIN 2

	imx6q-wandboard.dtb \

	imx6q-wandboard-revb1.dtb

dtb-$(CONFIG_SOC_IMX6SL) += \

	imx6sl-evk.dtb

	imx6sl-evk.dtb \

	imx6sl-warp.dtb

dtb-$(CONFIG_SOC_IMX6SX) += \

	imx6sx-sabreauto.dtb \

	imx6sx-sdb-reva.dtb \

	imx6sx-sdb.dtb

dtb-$(CONFIG_SOC_LS1021A) += \

	ls1021a-qds.dtb \

		mux-int-port = <1>;

		mux-ext-port = <4>;

	};

	wvga: display {

		model = "CLAA057VC01CW";

		bits-per-pixel = <16>;

		fsl,pcr = <0xfa208b80>;

		bus-width = <18>;

		native-mode = <&wvga_timings>;

		display-timings {

			wvga_timings: 640x480 {

				hactive = <640>;

				vactive = <480>;

				hback-porch = <45>;

				hfront-porch = <114>;

				hsync-len = <1>;

				vback-porch = <33>;

				vfront-porch = <11>;

				vsync-len = <1>;

				clock-frequency = <25200000>;

			};

		};

	};

};

&audmux {

			>;

		};

		pinctrl_lcd: lcdgrp {

			fsl,pins = <

				MX25_PAD_LD0__LD0		0xe0

				MX25_PAD_LD1__LD1		0xe0

				MX25_PAD_LD2__LD2		0xe0

				MX25_PAD_LD3__LD3		0xe0

				MX25_PAD_LD4__LD4		0xe0

				MX25_PAD_LD5__LD5		0xe0

				MX25_PAD_LD6__LD6		0xe0

				MX25_PAD_LD7__LD7		0xe0

				MX25_PAD_LD8__LD8		0xe0

				MX25_PAD_LD9__LD9		0xe0

				MX25_PAD_LD10__LD10		0xe0

				MX25_PAD_LD11__LD11		0xe0

				MX25_PAD_LD12__LD12		0xe0

				MX25_PAD_LD13__LD13		0xe0

				MX25_PAD_LD14__LD14		0xe0

				MX25_PAD_LD15__LD15		0xe0

				MX25_PAD_GPIO_E__LD16		0xe0

				MX25_PAD_GPIO_F__LD17		0xe0

				MX25_PAD_HSYNC__HSYNC		0xe0

				MX25_PAD_VSYNC__VSYNC		0xe0

				MX25_PAD_LSCLK__LSCLK		0xe0

				MX25_PAD_OE_ACD__OE_ACD		0xe0

				MX25_PAD_CONTRAST__CONTRAST	0xe0

			>;

		};

		pinctrl_uart1: uart1grp {

			fsl,pins = <

	};

};

&lcdc {

	display = <&wvga>;

	fsl,lpccr = <0x00a903ff>;

	fsl,lscr1 = <0x00120300>;

	fsl,dmacr = <0x00020010>;

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_lcd>;

	status = "okay";

};

&nfc {

	nand-on-flash-bbt;

	status = "okay";