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Commit 969af80f authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2016-08-25' of git://anongit.freedesktop.org/drm-intel into drm-fixes 

i915 fixes queue.

* tag 'drm-intel-fixes-2016-08-25' of git://anongit.freedesktop.org/drm-intel:
  drm/i915: Fix botched merge that downgrades CSR versions.
  drm/i915/skl: Ensure pipes with changed wms get added to the state
  drm/i915/gen9: Only copy WM results for changed pipes to skl_hw
  drm/i915/skl: Add support for the SAGV, fix underrun hangs
  drm/i915/gen6+: Interpret mailbox error flags
  drm/i915: Reattach comment, complete type specification
  drm/i915: Unconditionally flush any chipset buffers before execbuf
  drm/i915/gen9: Drop invalid WARN() during data rate calculation
  drm/i915/gen9: Initialize intel_state->active_crtcs during WM sanitization (v2)
parents 2b721f20 177d91aa

drivers/gpu/drm/i915/i915_drv.h

+11 −2
Original line number Diff line number Diff line
@@ -882,11 +882,12 @@ struct i915_gem_context { 


	struct i915_ctx_hang_stats hang_stats;



	/* Unique identifier for this context, used by the hw for tracking */

	unsigned long flags;

#define CONTEXT_NO_ZEROMAP		BIT(0)

#define CONTEXT_NO_ERROR_CAPTURE	BIT(1)

	unsigned hw_id;



	/* Unique identifier for this context, used by the hw for tracking */

	unsigned int hw_id;

	u32 user_handle;



	u32 ggtt_alignment;
@@ -1963,6 +1964,13 @@ struct drm_i915_private { 
	struct i915_suspend_saved_registers regfile;

	struct vlv_s0ix_state vlv_s0ix_state;



	enum {

		I915_SKL_SAGV_UNKNOWN = 0,

		I915_SKL_SAGV_DISABLED,

		I915_SKL_SAGV_ENABLED,

		I915_SKL_SAGV_NOT_CONTROLLED

	} skl_sagv_status;



	struct {

		/*

		 * Raw watermark latency values:
@@ -3591,6 +3599,7 @@ int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle); 
/* belongs in i915_gem_gtt.h */

static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)

{

	wmb();

	if (INTEL_GEN(dev_priv) < 6)

		intel_gtt_chipset_flush();

}

drivers/gpu/drm/i915/i915_gem_execbuffer.c

+3 −10
Original line number Diff line number Diff line
@@ -943,8 +943,6 @@ i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request *req, 
{

	const unsigned other_rings = ~intel_engine_flag(req->engine);

	struct i915_vma *vma;

	uint32_t flush_domains = 0;

	bool flush_chipset = false;

	int ret;



	list_for_each_entry(vma, vmas, exec_list) {
@@ -957,17 +955,12 @@ i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request *req, 
		}



		if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)

			flush_chipset |= i915_gem_clflush_object(obj, false);



		flush_domains |= obj->base.write_domain;

			i915_gem_clflush_object(obj, false);

	}



	if (flush_chipset)

	/* Unconditionally flush any chipset caches (for streaming writes). */

	i915_gem_chipset_flush(req->engine->i915);



	if (flush_domains & I915_GEM_DOMAIN_GTT)

		wmb();



	/* Unconditionally invalidate gpu caches and ensure that we do flush

	 * any residual writes from the previous batch.

	 */

drivers/gpu/drm/i915/i915_reg.h

+13 −0
Original line number Diff line number Diff line
@@ -7145,6 +7145,15 @@ enum { 


#define GEN6_PCODE_MAILBOX			_MMIO(0x138124)

#define   GEN6_PCODE_READY			(1<<31)

#define   GEN6_PCODE_ERROR_MASK			0xFF

#define     GEN6_PCODE_SUCCESS			0x0

#define     GEN6_PCODE_ILLEGAL_CMD		0x1

#define     GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2

#define     GEN6_PCODE_TIMEOUT			0x3

#define     GEN6_PCODE_UNIMPLEMENTED_CMD	0xFF

#define     GEN7_PCODE_TIMEOUT			0x2

#define     GEN7_PCODE_ILLEGAL_DATA		0x3

#define     GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10

#define	  GEN6_PCODE_WRITE_RC6VIDS		0x4

#define	  GEN6_PCODE_READ_RC6VIDS		0x5

#define     GEN6_ENCODE_RC6_VID(mv)		(((mv) - 245) / 5)
@@ -7166,6 +7175,10 @@ enum { 
#define   HSW_PCODE_DE_WRITE_FREQ_REQ		0x17

#define   DISPLAY_IPS_CONTROL			0x19

#define	  HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL	0x1A

#define   GEN9_PCODE_SAGV_CONTROL		0x21

#define     GEN9_SAGV_DISABLE			0x0

#define     GEN9_SAGV_IS_DISABLED		0x1

#define     GEN9_SAGV_ENABLE			0x3

#define GEN6_PCODE_DATA				_MMIO(0x138128)

#define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8

#define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT	16

drivers/gpu/drm/i915/intel_csr.c

+4 −4
Original line number Diff line number Diff line
@@ -41,15 +41,15 @@ 
 * be moved to FW_FAILED.

 */



#define I915_CSR_KBL "i915/kbl_dmc_ver1.bin"

#define I915_CSR_KBL "i915/kbl_dmc_ver1_01.bin"

MODULE_FIRMWARE(I915_CSR_KBL);

#define KBL_CSR_VERSION_REQUIRED	CSR_VERSION(1, 1)



#define I915_CSR_SKL "i915/skl_dmc_ver1.bin"

#define I915_CSR_SKL "i915/skl_dmc_ver1_26.bin"

MODULE_FIRMWARE(I915_CSR_SKL);

#define SKL_CSR_VERSION_REQUIRED	CSR_VERSION(1, 23)

#define SKL_CSR_VERSION_REQUIRED	CSR_VERSION(1, 26)



#define I915_CSR_BXT "i915/bxt_dmc_ver1.bin"

#define I915_CSR_BXT "i915/bxt_dmc_ver1_07.bin"

MODULE_FIRMWARE(I915_CSR_BXT);

#define BXT_CSR_VERSION_REQUIRED	CSR_VERSION(1, 7)

drivers/gpu/drm/i915/intel_display.c

+11 −0
Original line number Diff line number Diff line
@@ -13759,6 +13759,13 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state) 
		     intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco))

			dev_priv->display.modeset_commit_cdclk(state);



		/*

		 * SKL workaround: bspec recommends we disable the SAGV when we

		 * have more then one pipe enabled

		 */

		if (IS_SKYLAKE(dev_priv) && !skl_can_enable_sagv(state))

			skl_disable_sagv(dev_priv);



		intel_modeset_verify_disabled(dev);

	}
@@ -13832,6 +13839,10 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state) 
		intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state);

	}



	if (IS_SKYLAKE(dev_priv) && intel_state->modeset &&

	    skl_can_enable_sagv(state))

		skl_enable_sagv(dev_priv);



	drm_atomic_helper_commit_hw_done(state);



	if (intel_state->modeset)