Commit 964f6645 authored Jul 13, 2011 by Benjamin Herrenschmidt Committed by Dave Airlie Jul 25, 2011

drm/radeon: Add a rmb() in IH processing



We should have a read memory barrier between reading the WPTR from
memory and reading ring entries based on that value (ie, we need to
ensure both loads are done in order by the CPU).

It could be argued that the MMIO reads in r600_ack_irq() might be
enough to get that barrier but I prefer keeping an explicit one just
in case.

[airlied: fix evergreen + r/w mixup]

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

parent f1bece7f

drivers/gpu/drm/radeon/evergreen.c

+3 −0

Original line number	Diff line number	Diff line
		@@ -2759,6 +2759,9 @@ int evergreen_irq_process(struct radeon_device *rdev)
		return IRQ_NONE;
		}
		restart_ih:
		/* Order reading of wptr vs. reading of IH ring data */
		rmb();

		/* display interrupts */
		evergreen_irq_ack(rdev);

drivers/gpu/drm/radeon/r600.c

+3 −0

Original line number	Diff line number	Diff line
		@@ -3318,6 +3318,9 @@ int r600_irq_process(struct radeon_device *rdev)
		}

		restart_ih:
		/* Order reading of wptr vs. reading of IH ring data */
		rmb();

		/* display interrupts */
		r600_irq_ack(rdev);