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Commit 955d809b authored by Masahiro Yamada's avatar Masahiro Yamada Committed by Thierry Reding
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ARM: tegra: Remove redundant ARM_L1_CACHE_SHIFT_6 select 



These two are both ARMv7 SoCs.  They need not explicitly select
ARM_L1_CACHE_SHIFT_6 because it is enabled along with CPU_V7.

Refer to commit a092f2b1 ("ARM: 7291/1: cache: assume 64-byte L1
cachelines for ARMv7 CPUs").

Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent f55532a0

drivers/soc/tegra/Kconfig

+0 −2
Original line number Original line Diff line number Diff line
@@ -31,7 +31,6 @@ config ARCH_TEGRA_3x_SOC 
config ARCH_TEGRA_114_SOC

config ARCH_TEGRA_114_SOC

	bool "Enable support for Tegra114 family"

	bool "Enable support for Tegra114 family"

	select ARM_ERRATA_798181 if SMP

	select ARM_ERRATA_798181 if SMP

	select ARM_L1_CACHE_SHIFT_6

	select HAVE_ARM_ARCH_TIMER

	select HAVE_ARM_ARCH_TIMER

	select PINCTRL_TEGRA114

	select PINCTRL_TEGRA114

	select TEGRA_TIMER

	select TEGRA_TIMER
@@ -41,7 +40,6 @@ config ARCH_TEGRA_114_SOC 




config ARCH_TEGRA_124_SOC

config ARCH_TEGRA_124_SOC

	bool "Enable support for Tegra124 family"

	bool "Enable support for Tegra124 family"

	select ARM_L1_CACHE_SHIFT_6

	select HAVE_ARM_ARCH_TIMER

	select HAVE_ARM_ARCH_TIMER

	select PINCTRL_TEGRA124

	select PINCTRL_TEGRA124

	select TEGRA_TIMER

	select TEGRA_TIMER