Merge "msm: pcie: remove PCIe common PHY logic" (94fa85a3) · Commits · e / devices / android_kernel_fairphone_FP3

Documentation/devicetree/bindings/pci/msm_pcie.txt

+0 −11

Original line number	Diff line number	Diff line
		@@ -75,8 +75,6 @@ Optional Properties:
		- qcom,pcie-phy-ver: version of PCIe PHY.
		- qcom,phy-sequence: The initialization sequence to bring up the PCIe PHY.
		Should be specified in groups (offset, value, delay).
		- qcom,port-phy-sequence: The initialization sequence to bring up the
		PCIe port PHY.
		Should be specified in groups (offset, value, delay).
		- qcom,use-19p2mhz-aux-clk: The frequency of PCIe AUX clock is 19.2MHz.
		- qcom,boot-option: Bits that alter PCIe bus driver boot sequence.
		@@ -91,7 +89,6 @@ Optional Properties:
		- iommus: the phandle and stream IDs for the SMMU used by this root
		complex. This should be used in separate nodes from the main root
		complex nodes, and is the only property needed in that case.
		- qcom,common-phy: There is a common phy for all the Root Complexes.
		- qcom,smmu-exist: PCIe uses a SMMU.
		- qcom,smmu-sid-base: The base SMMU SID that PCIe bus driver will use to calculate
		and assign for each endpoint.
		@@ -214,13 +211,6 @@ Example:
		0x15c 0x06 0x00
		0x090 0x01 0x00
		0x808 0x03 0x00>;
		qcom,port-phy-sequence = <0x804 0x01 0x00
		0x034 0x14 0x00
		0x138 0x30 0x00
		0x048 0x0f 0x00
		0x15c 0x06 0x00
		0x090 0x01 0x00
		0x808 0x03 0x00>;
		perst-gpio = <&msmgpio 70 0>;
		wake-gpio = <&msmgpio 69 0>;
		clkreq-gpio = <&msmgpio 68 0>;
		@@ -272,7 +262,6 @@ Example:
		qcom,msi-gicm-base = <0x160>;
		qcom,ext-ref-clk;
		qcom,tlp-rd-size = <0x5>;
		qcom,common-phy;
		qcom,smmu-exist;
		qcom,smmu-sid-base = <0x1480>;
		qcom,ep-latency = <100>;

drivers/pci/host/pci-msm.c

+10 −121

Original line number	Diff line number	Diff line
		@@ -57,15 +57,11 @@

		#define PCS_BASE 0x800

		#define PCS_PORT(n, m) (PCS_BASE + n * m * 0x1000)
		#define PCS_PORT(n) (PCS_BASE + n * 0x1000)

		#define PCIE_N_SW_RESET(n, m) (PCS_PORT(n, m) + 0x00)
		#define PCIE_N_POWER_DOWN_CONTROL(n, m) (PCS_PORT(n, m) + 0x04)
		#define PCIE_N_PCS_STATUS(n, m) (PCS_PORT(n, m) + 0x174)

		#define PCIE_COM_SW_RESET 0x400
		#define PCIE_COM_POWER_DOWN_CONTROL 0x404
		#define PCIE_COM_PCS_READY_STATUS 0x448
		#define PCIE_N_SW_RESET(n) (PCS_PORT(n) + 0x00)
		#define PCIE_N_POWER_DOWN_CONTROL(n) (PCS_PORT(n) + 0x04)
		#define PCIE_N_PCS_STATUS(n) (PCS_PORT(n) + 0x174)

		#define PCIE20_PARF_SYS_CTRL 0x00
		#define PCIE20_PARF_PM_CTRL 0x20
		@@ -482,7 +478,6 @@ struct msm_pcie_dev_t {
		uint32_t smmu_sid_base;
		uint32_t n_fts;
		bool ext_ref_clk;
		bool common_phy;
		uint32_t ep_latency;
		uint32_t wr_halt_size;
		uint32_t cpl_timeout;
		@@ -518,9 +513,7 @@ struct msm_pcie_dev_t {
		u32 num_ep;
		bool pending_ep_reg;
		u32 phy_len;
		u32 port_phy_len;
		struct msm_pcie_phy_info_t *phy_sequence;
		struct msm_pcie_phy_info_t *port_phy_sequence;
		u32 ep_shadow[MAX_DEVICE_NUM][PCIE_CONF_SPACE_DW];
		u32 rc_shadow[PCIE_CONF_SPACE_DW];
		bool shadow_en;
		@@ -553,12 +546,6 @@ static u32 wr_mask;
		static u32 wr_value;
		static ulong corr_counter_limit = 5;

		/* counter to keep track if common PHY needs to be configured */
		static u32 num_rc_on;

		/* global lock for PCIe common PHY */
		static struct mutex com_phy_lock;

		/* Table to track info of PCIe devices */
		static struct msm_pcie_device_info
		msm_pcie_dev_tbl[MAX_RC_NUM * MAX_DEVICE_NUM];
		@@ -853,41 +840,9 @@ static void pcie_phy_init(struct msm_pcie_dev_t *dev)
		}
		}

		static void pcie_pcs_port_phy_init(struct msm_pcie_dev_t *dev)
		{
		int i;
		struct msm_pcie_phy_info_t *phy_seq;

		PCIE_DBG(dev, "RC%d: Initializing PCIe PHY Port\n", dev->rc_idx);

		if (dev->port_phy_sequence) {
		i = dev->port_phy_len;
		phy_seq = dev->port_phy_sequence;
		while (i--) {
		msm_pcie_write_reg(dev->phy,
		phy_seq->offset,
		phy_seq->val);
		if (phy_seq->delay)
		usleep_range(phy_seq->delay,
		phy_seq->delay + 1);
		phy_seq++;
		}
		}

		}

		static bool pcie_phy_is_ready(struct msm_pcie_dev_t *dev)
		{
		if (dev->phy_ver >= 0x20) {
		if (readl_relaxed(dev->phy +
		PCIE_N_PCS_STATUS(dev->rc_idx, dev->common_phy)) &
		BIT(6))
		return false;
		else
		return true;
		}

		if (!(readl_relaxed(dev->phy + PCIE_COM_PCS_READY_STATUS) & 0x1))
		if (readl_relaxed(dev->phy + PCIE_N_PCS_STATUS(dev->rc_idx)) & BIT(6))
		return false;
		else
		return true;
		@@ -1093,8 +1048,6 @@ static void msm_pcie_show_status(struct msm_pcie_dev_t *dev)
		dev->pending_ep_reg ? "true" : "false");
		PCIE_DBG_FS(dev, "phy_len is %d",
		dev->phy_len);
		PCIE_DBG_FS(dev, "port_phy_len is %d",
		dev->port_phy_len);
		PCIE_DBG_FS(dev, "disable_pc is %d",
		dev->disable_pc);
		PCIE_DBG_FS(dev, "l0s_supported is %s supported\n",
		@@ -1139,8 +1092,6 @@ static void msm_pcie_show_status(struct msm_pcie_dev_t *dev)
		dev->smmu_sid_base);
		PCIE_DBG_FS(dev, "n_fts: %d\n",
		dev->n_fts);
		PCIE_DBG_FS(dev, "common_phy: %d\n",
		dev->common_phy);
		PCIE_DBG_FS(dev, "ep_latency: %dms\n",
		dev->ep_latency);
		PCIE_DBG_FS(dev, "wr_halt_size: 0x%x\n",
		@@ -3400,31 +3351,6 @@ static int msm_pcie_get_resources(struct msm_pcie_dev_t *dev,
		dev->rc_idx);
		}

		of_get_property(pdev->dev.of_node, "qcom,port-phy-sequence", &size);
		if (size) {
		dev->port_phy_sequence = (struct msm_pcie_phy_info_t *)
		devm_kzalloc(&pdev->dev, size, GFP_KERNEL);

		if (dev->port_phy_sequence) {
		dev->port_phy_len =
		size / sizeof(*dev->port_phy_sequence);

		of_property_read_u32_array(pdev->dev.of_node,
		"qcom,port-phy-sequence",
		(unsigned int *)dev->port_phy_sequence,
		size / sizeof(dev->port_phy_sequence->offset));
		} else {
		PCIE_ERR(dev,
		"RC%d: Could not allocate memory for port phy init sequence.\n",
		dev->rc_idx);
		ret = -ENOMEM;
		goto out;
		}
		} else {
		PCIE_DBG(dev, "RC%d: port phy sequence is not present in DT\n",
		dev->rc_idx);
		}

		for (i = 0; i < MSM_PCIE_MAX_CLK; i++) {
		clk_info = &dev->clk[i];

		@@ -3753,14 +3679,9 @@ static int msm_pcie_enable(struct msm_pcie_dev_t *dev, u32 options)
		PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT));
		}

		mutex_lock(&com_phy_lock);
		/* init PCIe PHY */
		if (!num_rc_on)
		pcie_phy_init(dev);

		num_rc_on++;
		mutex_unlock(&com_phy_lock);

		if (options & PM_PIPE_CLK) {
		usleep_range(PHY_STABILIZATION_DELAY_US_MIN,
		PHY_STABILIZATION_DELAY_US_MAX);
		@@ -3795,8 +3716,6 @@ static int msm_pcie_enable(struct msm_pcie_dev_t *dev, u32 options)
		goto link_fail;
		}

		pcie_pcs_port_phy_init(dev);

		if (dev->ep_latency)
		usleep_range(dev->ep_latency * 1000, dev->ep_latency * 1000);

		@@ -3869,19 +3788,9 @@ static int msm_pcie_enable(struct msm_pcie_dev_t *dev, u32 options)
		gpio_set_value(dev->gpio[MSM_PCIE_GPIO_EP].num,
		1 - dev->gpio[MSM_PCIE_GPIO_EP].on);
		msm_pcie_write_reg(dev->phy,
		PCIE_N_SW_RESET(dev->rc_idx, dev->common_phy), 0x1);
		PCIE_N_SW_RESET(dev->rc_idx), 0x1);
		msm_pcie_write_reg(dev->phy,
		PCIE_N_POWER_DOWN_CONTROL(dev->rc_idx, dev->common_phy), 0);

		mutex_lock(&com_phy_lock);
		num_rc_on--;
		if (!num_rc_on && dev->common_phy) {
		PCIE_DBG(dev, "PCIe: RC%d is powering down the common phy\n",
		dev->rc_idx);
		msm_pcie_write_reg(dev->phy, PCIE_COM_SW_RESET, 0x1);
		msm_pcie_write_reg(dev->phy, PCIE_COM_POWER_DOWN_CONTROL, 0);
		}
		mutex_unlock(&com_phy_lock);
		PCIE_N_POWER_DOWN_CONTROL(dev->rc_idx), 0);

		msm_pcie_pipe_clk_deinit(dev);
		msm_pcie_clk_deinit(dev);
		@@ -3920,19 +3829,9 @@ static void msm_pcie_disable(struct msm_pcie_dev_t *dev, u32 options)
		dev->gpio[MSM_PCIE_GPIO_PERST].on);

		msm_pcie_write_reg(dev->phy,
		PCIE_N_SW_RESET(dev->rc_idx, dev->common_phy), 0x1);
		PCIE_N_SW_RESET(dev->rc_idx), 0x1);
		msm_pcie_write_reg(dev->phy,
		PCIE_N_POWER_DOWN_CONTROL(dev->rc_idx, dev->common_phy), 0);

		mutex_lock(&com_phy_lock);
		num_rc_on--;
		if (!num_rc_on && dev->common_phy) {
		PCIE_DBG(dev, "PCIe: RC%d is powering down the common phy\n",
		dev->rc_idx);
		msm_pcie_write_reg(dev->phy, PCIE_COM_SW_RESET, 0x1);
		msm_pcie_write_reg(dev->phy, PCIE_COM_POWER_DOWN_CONTROL, 0);
		}
		mutex_unlock(&com_phy_lock);
		PCIE_N_POWER_DOWN_CONTROL(dev->rc_idx), 0);

		if (options & PM_CLK) {
		msm_pcie_write_mask(dev->parf + PCIE20_PARF_PHY_CTRL, 0,
		@@ -5382,13 +5281,6 @@ static int msm_pcie_probe(struct platform_device *pdev)
		PCIE_DBG(&msm_pcie_dev[rc_idx], "n-fts: 0x%x.\n",
		msm_pcie_dev[rc_idx].n_fts);

		msm_pcie_dev[rc_idx].common_phy =
		of_property_read_bool((&pdev->dev)->of_node,
		"qcom,common-phy");
		PCIE_DBG(&msm_pcie_dev[rc_idx],
		"PCIe: RC%d: Common PHY does %s exist.\n",
		rc_idx, msm_pcie_dev[rc_idx].common_phy ? "" : "not");

		msm_pcie_dev[rc_idx].ext_ref_clk =
		of_property_read_bool((&pdev->dev)->of_node,
		"qcom,ext-ref-clk");
		@@ -5519,9 +5411,7 @@ static int msm_pcie_probe(struct platform_device *pdev)
		msm_pcie_dev[rc_idx].num_ep = 0;
		msm_pcie_dev[rc_idx].pending_ep_reg = false;
		msm_pcie_dev[rc_idx].phy_len = 0;
		msm_pcie_dev[rc_idx].port_phy_len = 0;
		msm_pcie_dev[rc_idx].phy_sequence = NULL;
		msm_pcie_dev[rc_idx].port_phy_sequence = NULL;
		msm_pcie_dev[rc_idx].event_reg = NULL;
		msm_pcie_dev[rc_idx].linkdown_counter = 0;
		msm_pcie_dev[rc_idx].link_turned_on_counter = 0;
		@@ -5730,7 +5620,6 @@ static int __init pcie_init(void)

		pcie_drv.rc_num = 0;
		mutex_init(&pcie_drv.drv_lock);
		mutex_init(&com_phy_lock);

		for (i = 0; i < MAX_RC_NUM; i++) {
		snprintf(rc_name, MAX_RC_NAME_LEN, "pcie%d-short", i);