Loading drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_2_2.c +1 −0 Original line number Diff line number Diff line Loading @@ -113,6 +113,7 @@ void dsi_ctrl_hw_kickoff_non_embedded_mode(struct dsi_ctrl_hw *ctrl, reg = DSI_R32(ctrl, DSI_DMA_FIFO_CTRL); reg |= BIT(20); reg |= BIT(16); reg |= 0x33;/* Set READ and WRITE watermark levels to maximum */ DSI_W32(ctrl, DSI_DMA_FIFO_CTRL, reg); DSI_W32(ctrl, DSI_DMA_CMD_OFFSET, cmd->offset); Loading drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_cmn.c +2 −3 Original line number Diff line number Diff line Loading @@ -618,9 +618,8 @@ void dsi_ctrl_hw_cmn_kickoff_command(struct dsi_ctrl_hw *ctrl, DSI_W32(ctrl, DSI_COMMAND_MODE_DMA_CTRL, reg); reg = DSI_R32(ctrl, DSI_DMA_FIFO_CTRL); reg &= ~BIT(20);/* Enable write watermark*/ reg &= ~BIT(16);/* Enable read watermark */ reg |= BIT(20);/* Disable write watermark*/ reg |= BIT(16);/* Disable read watermark */ DSI_W32(ctrl, DSI_DMA_FIFO_CTRL, reg); DSI_W32(ctrl, DSI_DMA_CMD_OFFSET, cmd->offset); Loading Loading
drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_2_2.c +1 −0 Original line number Diff line number Diff line Loading @@ -113,6 +113,7 @@ void dsi_ctrl_hw_kickoff_non_embedded_mode(struct dsi_ctrl_hw *ctrl, reg = DSI_R32(ctrl, DSI_DMA_FIFO_CTRL); reg |= BIT(20); reg |= BIT(16); reg |= 0x33;/* Set READ and WRITE watermark levels to maximum */ DSI_W32(ctrl, DSI_DMA_FIFO_CTRL, reg); DSI_W32(ctrl, DSI_DMA_CMD_OFFSET, cmd->offset); Loading
drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_cmn.c +2 −3 Original line number Diff line number Diff line Loading @@ -618,9 +618,8 @@ void dsi_ctrl_hw_cmn_kickoff_command(struct dsi_ctrl_hw *ctrl, DSI_W32(ctrl, DSI_COMMAND_MODE_DMA_CTRL, reg); reg = DSI_R32(ctrl, DSI_DMA_FIFO_CTRL); reg &= ~BIT(20);/* Enable write watermark*/ reg &= ~BIT(16);/* Enable read watermark */ reg |= BIT(20);/* Disable write watermark*/ reg |= BIT(16);/* Disable read watermark */ DSI_W32(ctrl, DSI_DMA_FIFO_CTRL, reg); DSI_W32(ctrl, DSI_DMA_CMD_OFFSET, cmd->offset); Loading