Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 937c57ea authored by Dmitry Osipenko's avatar Dmitry Osipenko Committed by Greg Kroah-Hartman
Browse files

clk: tegra: Fix duplicated SE clock entry 



[ Upstream commit 5bf5861d6ea6c3f4b38fc8fda2062b2dc44ac63d ]

The periph_clks[] array contains duplicated entry for Security Engine
clock which was meant to be defined for T210, but it wasn't added
properly. This patch corrects the T210 SE entry and fixes the following
error message on T114/T124: "Tegra clk 127: register failed with -17".

Fixes: dc37fec4 ("clk: tegra: periph: Add new periph clks and muxes for Tegra210")
Tested-by Nicolas Chauvet <kwizart@gmail.com>
Reported-by Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: default avatarDmitry Osipenko <digetx@gmail.com>
Link: https://lore.kernel.org/r/20201025224212.7790-1-digetx@gmail.com


Acked-by: default avatarThierry Reding <treding@nvidia.com>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent 45b2b650

drivers/clk/tegra/clk-id.h

+1 −0
Original line number Diff line number Diff line
@@ -233,6 +233,7 @@ enum clk_id { 
	tegra_clk_sdmmc4_8,

	tegra_clk_sdmmc4_9,

	tegra_clk_se,

	tegra_clk_se_10,

	tegra_clk_soc_therm,

	tegra_clk_soc_therm_8,

	tegra_clk_sor0,

drivers/clk/tegra/clk-tegra-periph.c

+1 −1
Original line number Diff line number Diff line
@@ -648,7 +648,7 @@ static struct tegra_periph_init_data periph_clks[] = { 
	INT8("host1x", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x_8),

	INT8("host1x", mux_pllc4_out1_pllc_pllc4_out2_pllp_clkm_plla_pllc4_out0, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x_9),

	INT8("se", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SE, 127, TEGRA_PERIPH_ON_APB, tegra_clk_se),

	INT8("se", mux_pllp_pllc2_c_c3_clkm, CLK_SOURCE_SE, 127, TEGRA_PERIPH_ON_APB, tegra_clk_se),

	INT8("se", mux_pllp_pllc2_c_c3_clkm, CLK_SOURCE_SE, 127, TEGRA_PERIPH_ON_APB, tegra_clk_se_10),

	INT8("2d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_2D, 21, 0, tegra_clk_gr2d_8),

	INT8("3d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_3D, 24, 0, tegra_clk_gr3d_8),

	INT8("vic03", mux_pllm_pllc_pllp_plla_pllc2_c3_clkm, CLK_SOURCE_VIC03, 178, 0, tegra_clk_vic03),